f3630dd95b
Parametrizable block design with selectable JESD physical layer between Xilinx Phy and ad_utilxcvr. |
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ad9081_fmca_ebz_bd.tcl |
f3630dd95b
Parametrizable block design with selectable JESD physical layer between Xilinx Phy and ad_utilxcvr. |
||
---|---|---|
.. | ||
ad9081_fmca_ebz_bd.tcl |