zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
62 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Adrian Costina 551319a670 Modified data mover to improve timing 2014-03-20 18:22:18 +02:00
library Modified data mover to improve timing 2014-03-20 18:22:18 +02:00
projects Fix the remaining issues 2014-03-20 14:36:01 +02:00
.gitignore added gitignore 2014-03-05 10:47:16 -05:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Update README.md 2014-03-13 14:03:15 -04:00

README.md

hdl

Analog Devices HDL libraries and projects

http://wiki.analog.com/resources/fpga/docs/hdl/github

http://wiki.analog.com/resources/fpga/docs/hdl/regmap