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pluto_hdl_adi/library/axi_logic_analyzer
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Istvan Csomortani ac2e5a9dac constraints: Update constraints 
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
 		2017-02-24 13:43:32 +02:00
..
Makefile axi_logic_analyzer: Initial commit 2017-01-31 16:23:56 +02:00
axi_logic_analyzer.v axi_logic_analyzer: Initial commit 2017-01-31 16:23:56 +02:00
axi_logic_analyzer_constr.xdc constraints: Update constraints 2017-02-24 13:43:32 +02:00
axi_logic_analyzer_ip.tcl axi_logic_analyzer: Initial commit 2017-01-31 16:23:56 +02:00
axi_logic_analyzer_reg.v axi_logic_analyzer: Initial commit 2017-01-31 16:23:56 +02:00
axi_logic_analyzer_trigger.v axi_logic_analyzer: Initial commit 2017-01-31 16:23:56 +02:00