116 lines
3.8 KiB
Verilog
116 lines
3.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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/*
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* Helper module for synchronizing a counter from one clock domain to another
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* using gray code. To work correctly the counter must not change its value by
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* more than one in one clock cycle in the source domain. I.e. the value may
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* change by either -1, 0 or +1.
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*/
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`timescale 1ns/100ps
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module sync_gray #(
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// Bit-width of the counter
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parameter DATA_WIDTH = 1,
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// Whether the input and output clock are asynchronous, if set to 0 the
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// synchronizer will be bypassed and out_count will be in_count.
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parameter ASYNC_CLK = 1)(
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input in_clk,
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input in_resetn,
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input [DATA_WIDTH-1:0] in_count,
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input out_resetn,
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input out_clk,
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output [DATA_WIDTH-1:0] out_count);
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generate if (ASYNC_CLK == 1) begin
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reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
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reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
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reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
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reg [DATA_WIDTH-1:0] out_count_m = 'h0;
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function [DATA_WIDTH-1:0] g2b;
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input [DATA_WIDTH-1:0] g;
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reg [DATA_WIDTH-1:0] b;
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integer i;
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begin
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b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
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for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
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b[i] = b[i + 1] ^ g[i];
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g2b = b;
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end
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endfunction
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function [DATA_WIDTH-1:0] b2g;
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input [DATA_WIDTH-1:0] b;
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reg [DATA_WIDTH-1:0] g;
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integer i;
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begin
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g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
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for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
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g[i] = b[i + 1] ^ b[i];
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b2g = g;
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end
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endfunction
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always @(posedge in_clk) begin
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if (in_resetn == 1'b0) begin
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cdc_sync_stage0 <= 'h00;
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end else begin
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cdc_sync_stage0 <= b2g(in_count);
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end
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end
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always @(posedge out_clk) begin
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if (out_resetn == 1'b0) begin
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cdc_sync_stage1 <= 'h00;
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cdc_sync_stage2 <= 'h00;
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out_count_m <= 'h00;
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end else begin
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cdc_sync_stage1 <= cdc_sync_stage0;
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cdc_sync_stage2 <= cdc_sync_stage1;
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out_count_m <= g2b(cdc_sync_stage2);
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end
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end
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assign out_count = out_count_m;
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end else begin
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assign out_count = in_count;
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end endgenerate
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endmodule
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