42 lines
2.0 KiB
Plaintext
42 lines
2.0 KiB
Plaintext
<: :>
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./sim/" :>
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<: setFileName ${ComponentName}_pkg :>
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<: setFileExtension ".sv" :>
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<: set id [get_property MODELPARAM_VALUE.ID] :>
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<: set mem_type [get_property MODELPARAM_VALUE.MEM_TYPE] :>
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<: set mem_size_log2 [get_property MODELPARAM_VALUE.MEM_SIZE_LOG2] :>
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<: set tx_or_rxn_path [get_property MODELPARAM_VALUE.TX_OR_RXN_PATH] :>
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<: set src_data_width [get_property MODELPARAM_VALUE.src_data_width] :>
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<: set dst_data_width [get_property MODELPARAM_VALUE.dst_data_width] :>
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<: set dst_cyclic_en [get_property MODELPARAM_VALUE.dst_cyclic_en] :>
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// boolean to intiger
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<: proc b2i {b} { if {$b==true} {return 1} else {return 0}} :>
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// C hex to verilog hex
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<: proc h2vh {a} { return [string replace $a 0 1 "'h"]} :>
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///////////////////////////////////////////////////////////////////////////
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//NOTE: This file has been automatically generated by Vivado.
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///////////////////////////////////////////////////////////////////////////
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package <=: ComponentName :>_pkg;
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///////////////////////////////////////////////////////////////////////////
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// These parameters are named after the component for use in your verification
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// environment.
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///////////////////////////////////////////////////////////////////////////
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parameter <=: ComponentName :>_ID = <=: $id :>;
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parameter <=: ComponentName :>_MEM_TYPE = <=: $mem_type :>;
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parameter <=: ComponentName :>_MEM_SIZE_LOG2 = <=: $mem_size_log2 :>;
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parameter <=: ComponentName :>_TX_OR_RXN_PATH = <=: b2i $tx_or_rxn_path :>;
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parameter <=: ComponentName :>_SRC_DATA_WIDTH = <=: b2i $src_data_width :>;
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parameter <=: ComponentName :>_DST_DATA_WIDTH = <=: b2i $dst_data_width :>;
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parameter <=: ComponentName :>_DST_CYCLIC_EN = <=: b2i $dst_cyclic_en :>;
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//////////////////////////////////////////////////////////////////////////
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endpackage : <=: ComponentName :>_pkg
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