66 lines
1.9 KiB
Verilog
66 lines
1.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_ext_sync #(
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parameter ENABLED = 1
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) (
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input clk,
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input ext_sync_arm,
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input ext_sync_disarm,
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input sync_in,
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output reg sync_armed = 1'b0
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);
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reg sync_in_d1 = 1'b0;
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reg sync_in_d2 = 1'b0;
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reg ext_sync_arm_d1 = 1'b0;
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reg ext_sync_disarm_d1 = 1'b0;
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// External sync
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always @(posedge clk) begin
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ext_sync_arm_d1 <= ext_sync_arm;
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ext_sync_disarm_d1 <= ext_sync_disarm;
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sync_in_d1 <= sync_in ;
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sync_in_d2 <= sync_in_d1;
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if (ENABLED == 1'b0) begin
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sync_armed <= 1'b0;
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end else if (~ext_sync_disarm_d1 & ext_sync_disarm) begin
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sync_armed <= 1'b0;
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end else if (~ext_sync_arm_d1 & ext_sync_arm) begin
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sync_armed <= 1'b1;
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end else if (~sync_in_d2 & sync_in_d1) begin
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sync_armed <= 1'b0;
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end
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end
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endmodule
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