139 lines
4.2 KiB
Verilog
139 lines
4.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Input must be RGB or CrYCb in that order, output is CrY/CbY
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`timescale 1ns/100ps
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module ad_ss_422to444 #(
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parameter CR_CB_N = 0,
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parameter DELAY_DATA_WIDTH = 16) (
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// 422 inputs
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input clk,
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input s422_de,
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input [DELAY_DATA_WIDTH-1:0] s422_sync,
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input [ 15:0] s422_data,
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// 444 outputs
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output reg [DELAY_DATA_WIDTH-1:0] s444_sync,
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output reg [ 23:0] s444_data);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// internal registers
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reg cr_cb_sel = 'd0;
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reg s422_de_d = 'd0;
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reg [DW:0] s422_sync_d = 'd0;
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reg s422_de_2d = 'd0;
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reg [7:0] s422_Y_d;
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reg [7:0] s422_CbCr_d;
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reg [7:0] s422_CbCr_2d;
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reg [ 8:0] s422_CbCr_avg;
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// internal wires
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wire [ 7:0] s422_Y;
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wire [ 7:0] s422_CbCr;
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// Input format is
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// [15:8] Cb/Cr
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// [ 7:0] Y
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//
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// Output format is
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// [23:15] Cr
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// [16: 8] Y
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// [ 7: 0] Cb
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assign s422_Y = s422_data[7:0];
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assign s422_CbCr = s422_data[15:8];
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// first data on de assertion is cb (0x0), then cr (0x1).
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// previous data is held when not current
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always @(posedge clk) begin
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if (s422_de_d == 1'b1) begin
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cr_cb_sel <= ~cr_cb_sel;
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end else begin
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cr_cb_sel <= CR_CB_N;
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end
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end
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// pipe line stages
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always @(posedge clk) begin
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s422_de_d <= s422_de;
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s422_sync_d <= s422_sync;
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s422_de_2d <= s422_de_d;
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s422_Y_d <= s422_Y;
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s422_CbCr_d <= s422_CbCr;
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s422_CbCr_2d <= s422_CbCr_d;
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end
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// If both the left and the right sample are valid do the average, otherwise
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// use the only valid.
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always @(s422_de_2d, s422_de, s422_CbCr, s422_CbCr_2d)
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begin
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if (s422_de == 1'b1 && s422_de_2d)
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s422_CbCr_avg <= s422_CbCr + s422_CbCr_2d;
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else if (s422_de == 1'b1)
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s422_CbCr_avg <= {s422_CbCr, 1'b0};
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else
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s422_CbCr_avg <= {s422_CbCr_2d, 1'b0};
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end
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// 444 outputs
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always @(posedge clk) begin
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s444_sync <= s422_sync_d;
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s444_data[15:8] <= s422_Y_d;
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if (cr_cb_sel) begin
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s444_data[23:16] <= s422_CbCr_d;
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s444_data[ 7: 0] <= s422_CbCr_avg[8:1];
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end else begin
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s444_data[23:16] <= s422_CbCr_avg[8:1];
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s444_data[ 7: 0] <= s422_CbCr_d;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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