152 lines
5.0 KiB
Verilog
152 lines
5.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module fifo_address_gray_pipelined (
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input m_axis_aclk,
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input m_axis_aresetn,
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input m_axis_ready,
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output reg m_axis_valid,
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output [ADDRESS_WIDTH-1:0] m_axis_raddr,
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output reg [ADDRESS_WIDTH:0] m_axis_level,
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input s_axis_aclk,
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input s_axis_aresetn,
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output reg s_axis_ready,
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input s_axis_valid,
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output reg s_axis_empty,
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output [ADDRESS_WIDTH-1:0] s_axis_waddr,
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output reg [ADDRESS_WIDTH:0] s_axis_room
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);
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parameter ADDRESS_WIDTH = 4;
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reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
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reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
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wire [ADDRESS_WIDTH:0] _s_axis_raddr;
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reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
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reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
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wire [ADDRESS_WIDTH:0] _m_axis_waddr;
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assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
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assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
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always @(*)
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begin
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if (s_axis_ready && s_axis_valid)
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_s_axis_waddr_next <= _s_axis_waddr + 1;
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else
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_s_axis_waddr_next <= _s_axis_waddr;
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end
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always @(posedge s_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0) begin
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_s_axis_waddr <= 'h00;
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end else begin
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_s_axis_waddr <= _s_axis_waddr_next;
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end
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end
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always @(*)
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begin
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if (m_axis_ready && m_axis_valid)
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_m_axis_raddr_next <= _m_axis_raddr + 1;
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else
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_m_axis_raddr_next <= _m_axis_raddr;
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end
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always @(posedge m_axis_aclk)
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begin
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if (m_axis_aresetn == 1'b0) begin
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_m_axis_raddr <= 'h00;
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end else begin
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_m_axis_raddr <= _m_axis_raddr_next;
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end
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end
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sync_gray #(
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.DATA_WIDTH(ADDRESS_WIDTH + 1)
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) i_waddr_sync (
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.in_clk(s_axis_aclk),
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.in_resetn(s_axis_aresetn),
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.out_clk(m_axis_aclk),
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.out_resetn(m_axis_aresetn),
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.in_count(_s_axis_waddr),
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.out_count(_m_axis_waddr)
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);
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sync_gray #(
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.DATA_WIDTH(ADDRESS_WIDTH + 1)
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) i_raddr_sync (
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.in_clk(m_axis_aclk),
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.in_resetn(m_axis_aresetn),
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.out_clk(s_axis_aclk),
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.out_resetn(s_axis_aresetn),
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.in_count(_m_axis_raddr),
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.out_count(_s_axis_raddr)
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);
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always @(posedge s_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0) begin
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s_axis_ready <= 1'b1;
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s_axis_empty <= 1'b1;
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s_axis_room <= 2**ADDRESS_WIDTH;
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end else begin
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s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
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_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
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s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
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s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH;
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end
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end
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always @(posedge m_axis_aclk)
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begin
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if (m_axis_aresetn == 1'b0) begin
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m_axis_valid <= 1'b0;
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m_axis_level <= 'h00;
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end else begin
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m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
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m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
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end
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end
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endmodule
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