203 lines
6.4 KiB
Verilog
203 lines
6.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// Xilinx ip cores are not fifo friendly and require a hard stop on the interface
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// valid & data can not change, if ready is deasserted (if they do you will have to
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// roll it back).
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_axis_inf_rx #(
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parameter DATA_WIDTH = 16) (
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// adi interface
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input clk,
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input rst,
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input valid,
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input last,
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input [DW:0] data,
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// xilinx interface
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output reg inf_valid,
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output reg inf_last,
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output reg [DW:0] inf_data,
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input inf_ready);
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localparam DW = DATA_WIDTH - 1;
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// internal registers
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reg [ 2:0] wcnt = 'd0;
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reg wlast_0 = 'd0;
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reg [DW:0] wdata_0 = 'd0;
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reg wlast_1 = 'd0;
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reg [DW:0] wdata_1 = 'd0;
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reg wlast_2 = 'd0;
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reg [DW:0] wdata_2 = 'd0;
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reg wlast_3 = 'd0;
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reg [DW:0] wdata_3 = 'd0;
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reg wlast_4 = 'd0;
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reg [DW:0] wdata_4 = 'd0;
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reg wlast_5 = 'd0;
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reg [DW:0] wdata_5 = 'd0;
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reg wlast_6 = 'd0;
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reg [DW:0] wdata_6 = 'd0;
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reg wlast_7 = 'd0;
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reg [DW:0] wdata_7 = 'd0;
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reg [ 2:0] rcnt = 'd0;
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// internal signals
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wire inf_ready_s;
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reg inf_last_s;
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reg [DW:0] inf_data_s;
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// write interface
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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wcnt <= 'd0;
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end else if (valid == 1'b1) begin
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wcnt <= wcnt + 1'b1;
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end
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if ((wcnt == 3'd0) && (valid == 1'b1)) begin
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wlast_0 <= last;
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wdata_0 <= data;
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end
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if ((wcnt == 3'd1) && (valid == 1'b1)) begin
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wlast_1 <= last;
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wdata_1 <= data;
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end
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if ((wcnt == 3'd2) && (valid == 1'b1)) begin
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wlast_2 <= last;
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wdata_2 <= data;
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end
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if ((wcnt == 3'd3) && (valid == 1'b1)) begin
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wlast_3 <= last;
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wdata_3 <= data;
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end
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if ((wcnt == 3'd4) && (valid == 1'b1)) begin
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wlast_4 <= last;
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wdata_4 <= data;
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end
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if ((wcnt == 3'd5) && (valid == 1'b1)) begin
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wlast_5 <= last;
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wdata_5 <= data;
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end
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if ((wcnt == 3'd6) && (valid == 1'b1)) begin
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wlast_6 <= last;
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wdata_6 <= data;
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end
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if ((wcnt == 3'd7) && (valid == 1'b1)) begin
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wlast_7 <= last;
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wdata_7 <= data;
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end
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end
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// read interface
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assign inf_ready_s = inf_ready | ~inf_valid;
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always @(rcnt or wlast_0 or wdata_0 or wlast_1 or wdata_1 or
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wlast_2 or wdata_2 or wlast_3 or wdata_3 or wlast_4 or wdata_4 or
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wlast_5 or wdata_5 or wlast_6 or wdata_6 or wlast_7 or wdata_7) begin
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case (rcnt)
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3'd0: begin
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inf_last_s = wlast_0;
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inf_data_s = wdata_0;
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end
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3'd1: begin
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inf_last_s = wlast_1;
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inf_data_s = wdata_1;
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end
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3'd2: begin
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inf_last_s = wlast_2;
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inf_data_s = wdata_2;
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end
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3'd3: begin
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inf_last_s = wlast_3;
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inf_data_s = wdata_3;
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end
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3'd4: begin
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inf_last_s = wlast_4;
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inf_data_s = wdata_4;
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end
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3'd5: begin
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inf_last_s = wlast_5;
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inf_data_s = wdata_5;
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end
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3'd6: begin
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inf_last_s = wlast_6;
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inf_data_s = wdata_6;
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end
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default: begin
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inf_last_s = wlast_7;
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inf_data_s = wdata_7;
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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rcnt <= 'd0;
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inf_valid <= 'd0;
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inf_last <= 'b0;
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inf_data <= 'd0;
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end else if (inf_ready_s == 1'b1) begin
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if (rcnt == wcnt) begin
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rcnt <= rcnt;
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inf_valid <= 1'd0;
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inf_last <= 1'b0;
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inf_data <= 'd0;
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end else begin
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rcnt <= rcnt + 1'b1;
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inf_valid <= 1'b1;
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inf_last <= inf_last_s;
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inf_data <= inf_data_s;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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