Istvan Csomortani 318dcbb5d9 adrv9371x: Set up the defualt clock output control ... The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default. The OUTCLK frequency is the same as the REFCLK. The main reason of this modification is that the links should come up without any DPR access, after power up, using the default reference clock configuration (122.88 MHz).		2018-04-11 15:09:54 +03:00
..
adrv9371x_bd.tcl	adrv9371x: Set up the defualt clock output control	2018-04-11 15:09:54 +03:00
adrv9371x_qsys.tcl	adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled	2017-10-04 11:29:09 +01:00