pluto_hdl_adi/library/axi_mc_speed/debouncer.v

103 lines
4.1 KiB
Verilog

// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
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// - Redistributions in binary form must reproduce the above copyright
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// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : debouncer.v
// MODULE NAME : debouncer
// AUTHOR : ACozma
// AUTHOR'S EMAIL : andrei.cozma@analog.com
// -----------------------------------------------------------------------------
// KEYWORDS :
// -----------------------------------------------------------------------------
// PURPOSE : Module used for debouncing input signals
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Synthesizable (y/n) : y
// Target Device :
// Other :
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
module debouncer
//----------- Paramters Declarations -------------------------------------------
#(
parameter DEBOUNCER_LEN = 4
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input rst_i,
input sig_i,
output reg sig_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [DEBOUNCER_LEN-1:0] shift_reg;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
always @(posedge clk_i)
begin
if(rst_i == 1)
begin
shift_reg <= 0;
sig_o <= 0;
end
else
begin
shift_reg <= {shift_reg[DEBOUNCER_LEN-2:0], sig_i};
if(shift_reg == {DEBOUNCER_LEN{1'b1}})
begin
sig_o <= 1'b1;
end
else if(shift_reg == {DEBOUNCER_LEN{1'b0}})
begin
sig_o <= 1'b0;
end
end
end
endmodule