492 lines
14 KiB
Verilog
492 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_usb_fx3 (
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// gpif ii
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dma_rdy,
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dma_wmk,
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fifo_rdy,
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pclk, //output clk 100 Mhz and 180 phase shift
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data,
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addr, //output fifo address
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slcs_n, //output chip select
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slrd_n, //output read select
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sloe_n, //output output enable select
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slwr_n, //output write select
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pktend_n, //output pkt end
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epswitch_n, //output EP Switch
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// irq
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irq,
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// DEBUG
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debug_fx32dma,
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debug_dma2fx3,
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debug_status,
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// s2mm
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s_axis_tdata,
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s_axis_tkeep,
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s_axis_tlast,
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s_axis_tvalid,
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s_axis_tready,
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// mm2s
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m_axis_tready,
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m_axis_tdata,
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m_axis_tkeep,
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m_axis_tlast,
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m_axis_tvalid,
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// axi lite
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awprot,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arprot,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rready);
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// gpif ii
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input dma_rdy;
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input dma_wmk;
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input [ 3:0] fifo_rdy;
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output pclk;
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inout [31:0] data;
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output [ 1:0] addr;
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output slcs_n;
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output slrd_n;
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output sloe_n;
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output slwr_n;
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output pktend_n;
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output epswitch_n;
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// DEBUG
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output [74:0] debug_fx32dma;
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output [73:0] debug_dma2fx3;
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output [14:0] debug_status;
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// irq
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output irq;
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// s2mm
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input [31:0] s_axis_tdata;
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input [ 3:0] s_axis_tkeep;
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input s_axis_tlast;
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input s_axis_tvalid;
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output s_axis_tready;
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// mm2s
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input m_axis_tready;
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output [31:0] m_axis_tdata;
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output [ 3:0] m_axis_tkeep;
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output m_axis_tlast;
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output m_axis_tvalid;
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// axi lite
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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input [ 2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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input [ 2:0] s_axi_arprot;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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// internal clocks & resets
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire [13:0] up_raddr;
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wire [31:0] up_rdata;
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wire up_rack;
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wire up_wack;
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wire up_wreq;
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wire [13:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_rreq_s;
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wire [ 7:0] fifo0_header_size;
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wire [15:0] fifo0_buffer_size;
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wire [ 7:0] fifo1_header_size;
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wire [15:0] fifo1_buffer_size;
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wire [ 7:0] fifo2_header_size;
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wire [15:0] fifo2_buffer_size;
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wire [ 7:0] fifo3_header_size;
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wire [15:0] fifo3_buffer_size;
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wire [ 7:0] fifo4_header_size;
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wire [15:0] fifo4_buffer_size;
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wire [ 7:0] fifo5_header_size;
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wire [15:0] fifo5_buffer_size;
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wire [ 7:0] fifo6_header_size;
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wire [15:0] fifo6_buffer_size;
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wire [ 7:0] fifo7_header_size;
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wire [15:0] fifo7_buffer_size;
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wire [ 7:0] fifo8_header_size;
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wire [15:0] fifo8_buffer_size;
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wire [ 7:0] fifo9_header_size;
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wire [15:0] fifo9_buffer_size;
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wire [ 7:0] fifoa_header_size;
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wire [15:0] fifoa_buffer_size;
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wire fifo0_direction;
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wire fifo1_direction;
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wire fifo2_direction;
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wire fifo3_direction;
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wire fifo4_direction;
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wire fifo5_direction;
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wire fifo6_direction;
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wire fifo7_direction;
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wire fifo8_direction;
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wire fifo9_direction;
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wire fifoa_direction;
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wire [10:0] fifo_direction;
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wire fx32dma_valid;
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wire fx32dma_ready;
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wire [31:0] fx32dma_data;
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wire fx32dma_sop;
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wire fx32dma_eop;
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wire dma2fx3_ready;
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wire dma2fx3_valid;
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wire [31:0] dma2fx3_data;
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wire dma2fx3_eop;
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wire [ 2:0] test_mode_tpm;
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wire [ 2:0] test_mode_tpg;
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wire monitor_error;
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wire eot_fx32dma;
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wire eot_dma2fx3;
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wire error;
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wire [ 4:0] fifo_num;
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wire [10:0] fifo_ready;
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wire [31:0] length_fx32dma;
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wire [31:0] length_dma2fx3;
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wire trig;
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wire zlp;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign pclk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign fifo_direction = {fifo9_direction, fifo8_direction, fifo7_direction, fifo6_direction, fifo5_direction, fifo4_direction, fifo3_direction, fifo2_direction, fifo1_direction, fifo0_direction};
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// DEBUG
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assign debug_dma2fx3 = {s_axis_tdata, dma2fx3_data, s_axis_tkeep, s_axis_tlast, s_axis_tvalid, s_axis_tready, dma2fx3_ready, dma2fx3_valid, dma2fx3_eop};
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assign debug_fx32dma = {fx32dma_eop, m_axis_tdata, fx32dma_data, m_axis_tkeep, m_axis_tlast, m_axis_tvalid, m_axis_tready, fx32dma_ready, fx32dma_valid, fx32dma_sop};
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assign debug_status = {irq, error, monitor_error, test_mode_tpg, test_mode_tpm, trig, fifo_num};
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// packetizer, TPM/TPG and DMA interface
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axi_usb_fx3_core ep_packetizer(
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.clk(pclk),
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.reset(!up_rstn),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tlast(s_axis_tlast),
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.s_axis_tready(s_axis_tready),
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.s_axis_tvalid(s_axis_tvalid),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tkeep(m_axis_tkeep),
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.m_axis_tlast(m_axis_tlast),
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.m_axis_tready(m_axis_tready),
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.m_axis_tvalid(m_axis_tvalid),
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.fifo0_header_size(fifo0_header_size),
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.fifo0_buffer_size(fifo0_buffer_size),
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.fifo1_header_size(fifo1_header_size),
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.fifo1_buffer_size(fifo1_buffer_size),
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.fifo2_header_size(fifo2_header_size),
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.fifo2_buffer_size(fifo2_buffer_size),
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.fifo3_header_size(fifo3_header_size),
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.fifo3_buffer_size(fifo3_buffer_size),
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.fifo4_header_size(fifo4_header_size),
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.fifo4_buffer_size(fifo4_buffer_size),
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.fifo5_header_size(fifo5_header_size),
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.fifo5_buffer_size(fifo5_buffer_size),
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.fifo6_header_size(fifo6_header_size),
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.fifo6_buffer_size(fifo6_buffer_size),
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.fifo7_header_size(fifo7_header_size),
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.fifo7_buffer_size(fifo7_buffer_size),
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.fifo8_header_size(fifo8_header_size),
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.fifo8_buffer_size(fifo8_buffer_size),
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.fifo9_header_size(fifo9_header_size),
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.fifo9_buffer_size(fifo9_buffer_size),
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.fifoa_header_size(fifoa_header_size),
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.fifoa_buffer_size(fifoa_buffer_size),
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.length_fx32dma(length_fx32dma),
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.length_dma2fx3(length_dma2fx3),
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.fx32dma_valid(fx32dma_valid),
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.fx32dma_ready(fx32dma_ready),
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.fx32dma_data(fx32dma_data),
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.fx32dma_sop(fx32dma_sop),
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.fx32dma_eop(fx32dma_eop),
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.dma2fx3_ready(dma2fx3_ready),
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.dma2fx3_valid(dma2fx3_valid),
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.dma2fx3_data(dma2fx3_data),
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.dma2fx3_eop(dma2fx3_eop),
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.error(error),
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.eot_fx32dma(eot_fx32dma),
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.eot_dma2fx3(eot_dma2fx3),
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.test_mode_tpm(test_mode_tpm),
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.test_mode_tpg(test_mode_tpg),
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.monitor_error(monitor_error),
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.zlp(zlp),
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.fifo_num(fifo_num));
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// register map
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axi_usb_fx3_reg fx3_registers(
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.fifo_rdy(fifo_ready),
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.eot_fx32dma(eot_fx32dma),
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.eot_dma2fx3(eot_dma2fx3),
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.trig(trig),
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.zlp(zlp),
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.fifo_num(fifo_num),
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.error(error),
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.test_mode_tpm(test_mode_tpm),
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.test_mode_tpg(test_mode_tpg),
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.monitor_error(monitor_error),
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.irq(irq),
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.fifo0_direction(fifo0_direction),
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.fifo0_header_size(fifo0_header_size),
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.fifo0_buffer_size(fifo0_buffer_size),
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.fifo1_direction(fifo1_direction),
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.fifo1_header_size(fifo1_header_size),
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.fifo1_buffer_size(fifo1_buffer_size),
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.fifo2_direction(fifo2_direction),
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.fifo2_header_size(fifo2_header_size),
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.fifo2_buffer_size(fifo2_buffer_size),
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.fifo3_direction(fifo3_direction),
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.fifo3_header_size(fifo3_header_size),
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.fifo3_buffer_size(fifo3_buffer_size),
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.fifo4_direction(fifo4_direction),
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.fifo4_header_size(fifo4_header_size),
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.fifo4_buffer_size(fifo4_buffer_size),
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.fifo5_direction(fifo5_direction),
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.fifo5_header_size(fifo5_header_size),
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.fifo5_buffer_size(fifo5_buffer_size),
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.fifo6_direction(fifo6_direction),
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.fifo6_header_size(fifo6_header_size),
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.fifo6_buffer_size(fifo6_buffer_size),
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.fifo7_direction(fifo7_direction),
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.fifo7_header_size(fifo7_header_size),
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.fifo7_buffer_size(fifo7_buffer_size),
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.fifo8_direction(fifo8_direction),
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.fifo8_header_size(fifo8_header_size),
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.fifo8_buffer_size(fifo8_buffer_size),
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.fifo9_direction(fifo9_direction),
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.fifo9_header_size(fifo9_header_size),
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.fifo9_buffer_size(fifo9_buffer_size),
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.fifoa_direction(fifoa_direction),
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.fifoa_header_size(fifoa_header_size),
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.fifoa_buffer_size(fifoa_buffer_size),
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.length_fx32dma(length_fx32dma),
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.length_dma2fx3(length_dma2fx3),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack));
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// GPIF II interface
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axi_usb_fx3_if fx3_if(
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.pclk(pclk), //output clk 100 Mhz and 180 phase shift
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.reset_n(up_rstn),
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.dma_rdy(dma_rdy),
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.dma_wmk(dma_wmk),
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.fifo_rdy(fifo_rdy),
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.data(data),
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.addr(addr), //output fifo address
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.slcs_n(slcs_n), //output chip select
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.slrd_n(slrd_n), //output read select
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.sloe_n(sloe_n), //output output enable select
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.slwr_n(slwr_n), //output write select
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.pktend_n(pktend_n), //output pkt end
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.epswitch_n(epswitch_n), //output pkt end
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.fifo_ready(fifo_ready),
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.fifo_num(fifo_num),
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.fifo_direction(fifo_direction),
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.trig(trig),
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.fx32dma_valid(fx32dma_valid),
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.fx32dma_ready(fx32dma_ready),
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.fx32dma_data(fx32dma_data),
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.fx32dma_sop(fx32dma_sop),
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.fx32dma_eop(fx32dma_eop),
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.eot_fx32dma(eot_fx32dma),
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.dma2fx3_ready(dma2fx3_ready),
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.dma2fx3_valid(dma2fx3_valid),
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.dma2fx3_data(dma2fx3_data),
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.dma2fx3_eop(dma2fx3_eop));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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|
.up_waddr (up_waddr),
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|
.up_wdata (up_wdata),
|
|
.up_wack (up_wack),
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|
.up_rreq (up_rreq),
|
|
.up_raddr (up_raddr),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
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|
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|
endmodule
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// ***************************************************************************
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// ***************************************************************************
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