261 lines
9.1 KiB
Verilog
261 lines
9.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9122_channel #(
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parameter CHANNEL_ID = 32'h0,
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parameter DATAPATH_DISABLE = 0) (
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// dac interface
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input dac_div_clk,
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input dac_rst,
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output reg dac_enable,
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output reg [63:0] dac_data,
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output reg [ 3:0] dac_frame,
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input [63:0] dma_data,
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// processor interface
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input dac_data_frame,
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input dac_data_sync,
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input dac_dds_format,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack);
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// internal registers
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reg [15:0] dac_dds_phase_0_0 = 'd0;
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reg [15:0] dac_dds_phase_0_1 = 'd0;
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reg [15:0] dac_dds_phase_1_0 = 'd0;
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reg [15:0] dac_dds_phase_1_1 = 'd0;
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reg [15:0] dac_dds_phase_2_0 = 'd0;
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reg [15:0] dac_dds_phase_2_1 = 'd0;
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reg [15:0] dac_dds_phase_3_0 = 'd0;
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reg [15:0] dac_dds_phase_3_1 = 'd0;
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reg [15:0] dac_dds_incr_0 = 'd0;
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reg [15:0] dac_dds_incr_1 = 'd0;
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reg [63:0] dac_dds_data = 'd0;
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// internal signals
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wire [15:0] dac_dds_data_0_s;
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wire [15:0] dac_dds_data_1_s;
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wire [15:0] dac_dds_data_2_s;
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wire [15:0] dac_dds_data_3_s;
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wire [15:0] dac_dds_scale_1_s;
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wire [15:0] dac_dds_init_1_s;
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wire [15:0] dac_dds_incr_1_s;
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wire [15:0] dac_dds_scale_2_s;
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wire [15:0] dac_dds_init_2_s;
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wire [15:0] dac_dds_incr_2_s;
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wire [15:0] dac_pat_data_1_s;
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wire [15:0] dac_pat_data_2_s;
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wire [ 3:0] dac_data_sel_s;
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// dac data select
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always @(posedge dac_div_clk) begin
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dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
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case (dac_data_sel_s)
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4'h2: dac_data <= dma_data;
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4'ha, 4'h1: dac_data <= {dac_pat_data_2_s, dac_pat_data_1_s,
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dac_pat_data_2_s, dac_pat_data_1_s};
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default: dac_data <= dac_dds_data;
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endcase
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if (dac_data_sel_s == 4'h1) begin
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dac_frame <= 4'b0101;
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end else begin
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dac_frame <= {3'd0, dac_data_frame};
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end
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end
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// single channel dds
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always @(posedge dac_div_clk) begin
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if (dac_data_sync == 1'b1) begin
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dac_dds_phase_0_0 <= dac_dds_init_1_s;
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dac_dds_phase_0_1 <= dac_dds_init_2_s;
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dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
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dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
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dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
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dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
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dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
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dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
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dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0};
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dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0};
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dac_dds_data <= 64'd0;
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end else begin
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dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
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dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
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dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
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dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
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dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
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dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
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dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
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dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
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dac_dds_incr_0 <= dac_dds_incr_0;
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dac_dds_incr_1 <= dac_dds_incr_1;
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dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s,
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dac_dds_data_1_s, dac_dds_data_0_s};
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end
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end
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generate
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if (DATAPATH_DISABLE == 1) begin
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assign dac_dds_data_0_s = 16'd0;
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end else begin
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ad_dds i_dds_0 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_0_0),
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.dds_scale_0 (dac_dds_scale_1_s),
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.dds_phase_1 (dac_dds_phase_0_1),
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.dds_scale_1 (dac_dds_scale_2_s),
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.dds_data (dac_dds_data_0_s));
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end
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endgenerate
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generate
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if (DATAPATH_DISABLE == 1) begin
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assign dac_dds_data_1_s = 16'd0;
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end else begin
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ad_dds i_dds_1 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_1_0),
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.dds_scale_0 (dac_dds_scale_1_s),
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.dds_phase_1 (dac_dds_phase_1_1),
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.dds_scale_1 (dac_dds_scale_2_s),
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.dds_data (dac_dds_data_1_s));
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end
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endgenerate
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generate
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if (DATAPATH_DISABLE == 1) begin
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assign dac_dds_data_2_s = 16'd0;
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end else begin
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ad_dds i_dds_2 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_2_0),
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.dds_scale_0 (dac_dds_scale_1_s),
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.dds_phase_1 (dac_dds_phase_2_1),
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.dds_scale_1 (dac_dds_scale_2_s),
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.dds_data (dac_dds_data_2_s));
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end
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endgenerate
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generate
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if (DATAPATH_DISABLE == 1) begin
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assign dac_dds_data_3_s = 16'd0;
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end else begin
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ad_dds i_dds_3 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_3_0),
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.dds_scale_0 (dac_dds_scale_1_s),
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.dds_phase_1 (dac_dds_phase_3_1),
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.dds_scale_1 (dac_dds_scale_2_s),
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.dds_data (dac_dds_data_3_s));
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end
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endgenerate
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// single channel processor
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up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
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.dac_clk (dac_div_clk),
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.dac_rst (dac_rst),
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.dac_dds_scale_1 (dac_dds_scale_1_s),
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.dac_dds_init_1 (dac_dds_init_1_s),
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.dac_dds_incr_1 (dac_dds_incr_1_s),
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.dac_dds_scale_2 (dac_dds_scale_2_s),
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.dac_dds_init_2 (dac_dds_init_2_s),
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.dac_dds_incr_2 (dac_dds_incr_2_s),
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.dac_pat_data_1 (dac_pat_data_1_s),
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.dac_pat_data_2 (dac_pat_data_2_s),
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.dac_data_sel (dac_data_sel_s),
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.dac_iq_mode (),
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.dac_iqcor_enb (),
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.dac_iqcor_coeff_1 (),
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.dac_iqcor_coeff_2 (),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_interpolation_m (),
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.up_usr_interpolation_n (),
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.dac_usr_datatype_be (1'b0),
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.dac_usr_datatype_signed (1'b1),
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.dac_usr_datatype_shift (8'd0),
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.dac_usr_datatype_total_bits (8'd16),
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.dac_usr_datatype_bits (8'd16),
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.dac_usr_interpolation_m (16'd1),
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.dac_usr_interpolation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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