Istvan Csomortani 758c617c77 common/up_* : Make up_rstn synchronous to up_clk ... The up_rstn is driven by s_axi_resetn, which is generated by a Processor System Reset module. (connected to port peripheral_aresetn) Therefor using this reset signal as an asynchronous reset is redundant, and a bad design practice at the same time. Asynchronous reset should be used if it's inevitable.		2018-04-11 15:09:54 +03:00
..
ad_data_clk.v	library/xilinx- lvds/cmos integration	2017-07-24 16:28:50 -04:00
ad_data_in.v	library/xilinx/common- add iodelay group	2017-07-25 10:22:52 -04:00
ad_data_out.v	library/xilinx/common- add iodelay group	2017-07-25 10:22:52 -04:00
ad_iobuf.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
ad_mmcm_drp.v	common/up_* : Make up_rstn synchronous to up_clk	2018-04-11 15:09:54 +03:00
ad_mul.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
ad_rst_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00
ad_serdes_clk.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
ad_serdes_in.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
ad_serdes_out.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
up_clock_mon_constr.xdc	up_clock_mon: Remove extra hold register	2017-05-23 11:16:07 +02:00
up_xfer_cntrl_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00
up_xfer_status_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00