507 lines
14 KiB
Verilog
507 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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input uart_sin,
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output uart_sout,
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output ddr4_act_n,
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output [16:0] ddr4_addr,
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output [ 1:0] ddr4_ba,
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output [ 0:0] ddr4_bg,
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output ddr4_ck_p,
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output ddr4_ck_n,
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output [ 0:0] ddr4_cke,
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output [ 0:0] ddr4_cs_n,
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inout [ 7:0] ddr4_dm_n,
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inout [63:0] ddr4_dq,
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inout [ 7:0] ddr4_dqs_p,
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inout [ 7:0] ddr4_dqs_n,
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output [ 0:0] ddr4_odt,
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output ddr4_reset_n,
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output mdio_mdc,
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inout mdio_mdio,
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input phy_clk_p,
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input phy_clk_n,
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output phy_rst_n,
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input phy_rx_p,
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input phy_rx_n,
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output phy_tx_p,
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output phy_tx_n,
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inout [16:0] gpio_bd,
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output iic_rstn,
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inout iic_scl,
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inout iic_sda,
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input vadj_1v8_pgood,
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// FMCp IOs
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//
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output [3:0] adf4371_cs,
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output adf4371_sclk,
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inout adf4371_sdio,
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output adrf5020_ctrl,
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input [2:0] fpga_clk_m2c_n,
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input [2:0] fpga_clk_m2c_p,
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input fpga_clk_m2c_0_replica_n,
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input fpga_clk_m2c_0_replica_p,
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output fpga_sysref_c2m_n,
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output fpga_sysref_c2m_p,
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input fpga_sysref_m2c_n,
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input fpga_sysref_m2c_p,
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output [15:0] c2m_n,
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output [15:0] c2m_p,
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input [15:0] m2c_n,
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input [15:0] m2c_p,
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output [3:0] mxfe_syncin_n,
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output [7:0] mxfe_syncin_p,
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input [3:0] mxfe_syncout_n,
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input [7:0] mxfe_syncout_p,
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inout hmc7043_gpio,
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output hmc7043_reset,
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output hmc7043_sclk,
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inout hmc7043_sdata,
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output hmc7043_slen,
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output [4:1] hmc425a_v,
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output [3:0] mxfe_sclk,
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output [3:0] mxfe_cs,
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input [3:0] mxfe_miso,
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output [3:0] mxfe_mosi,
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output [3:0] mxfe_reset,
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output [3:0] mxfe_rx_en0,
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output [3:0] mxfe_rx_en1,
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output [3:0] mxfe_tx_en0,
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output [3:0] mxfe_tx_en1,
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inout [8:0] mxfe0_gpio,
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inout [8:0] mxfe1_gpio,
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inout [8:0] mxfe2_gpio,
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inout [8:0] mxfe3_gpio,
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// PMOD1 for calibration board
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output pmod1_adc_sync_n,
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output pmod1_adc_sdi,
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input pmod1_adc_sdo,
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output pmod1_adc_sclk,
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output pmod1_5045_v2,
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output pmod1_5045_v1,
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output pmod1_ctrl_ind,
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output pmod1_ctrl_rx_combined
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);
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// internal signals
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wire [127:0] gpio_i;
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wire [127:0] gpio_o;
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wire [127:0] gpio_t;
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wire spi_clk;
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wire [ 7:0] spi_csn;
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wire spi_mosi;
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wire spi_miso;
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wire spi_4371_miso;
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wire spi_hmc_miso;
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wire spi_2_clk;
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wire [ 7:0] spi_2_csn;
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wire spi_2_mosi;
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wire spi_2_miso;
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wire spi_3_clk;
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wire [ 7:0] spi_3_csn;
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wire spi_3_mosi;
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wire spi_3_miso;
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wire ref_clk;
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wire sysref;
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wire [3:0] link0_tx_syncin;
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wire [3:0] link0_rx_syncout;
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wire [3:0] link1_tx_syncin;
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wire [3:0] link1_rx_syncout;
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wire fpga_clk_m2c_4;
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wire device_clk;
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wire ext_sync_at_sysref;
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reg ext_sync_ms = 1'b0;
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reg ext_sync_noms = 1'b0;
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reg ext_sync_noms_d1 = 1'b0;
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assign iic_rstn = 1'b1;
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// instantiations
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// Link 1 SYNC differential lines
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genvar i;
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generate
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for(i=0;i<=3;i=i+1) begin : g_buffers
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IBUFDS i_ibufds_syncin (
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.I (mxfe_syncout_p[2*i+1]),
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.IB (mxfe_syncout_n[i]),
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.O (link1_tx_syncin[i]));
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OBUFDS i_obufds_syncout (
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.I (link1_rx_syncout[i]),
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.O (mxfe_syncin_p[2*i+1]),
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.OB (mxfe_syncin_n[i]));
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end
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endgenerate
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// Link 0 SYNC single ended lines
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assign mxfe_syncin_p[0] = link0_rx_syncout[0];
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assign mxfe_syncin_p[2] = link0_rx_syncout[1];
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assign mxfe_syncin_p[4] = link0_rx_syncout[2];
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assign mxfe_syncin_p[6] = link0_rx_syncout[3];
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assign link0_tx_syncin[0] = mxfe_syncout_p[0];
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assign link0_tx_syncin[1] = mxfe_syncout_p[2];
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assign link0_tx_syncin[2] = mxfe_syncout_p[4];
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assign link0_tx_syncin[3] = mxfe_syncout_p[6];
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IBUFDS_GTE4 i_ibufds_ref_clk (
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.CEB (1'd0),
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.I (fpga_clk_m2c_p[0]),
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.IB (fpga_clk_m2c_n[0]),
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.O (ref_clk),
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.ODIV2 ());
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IBUFDS_GTE4 i_ibufds_ref_clk_replica (
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.CEB (1'd0),
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.I (fpga_clk_m2c_0_replica_p),
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.IB (fpga_clk_m2c_0_replica_n),
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.O (ref_clk_replica),
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.ODIV2 ());
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IBUFDS i_ibufds_sysref (
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.I (fpga_sysref_m2c_p),
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.IB (fpga_sysref_m2c_n),
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.O (sysref));
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OBUFDS i_obufds_sysref (
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.O (fpga_sysref_c2m_p),
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.OB (fpga_sysref_c2m_n),
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.I (sysref));
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IBUFDS i_ibufds_rx_device_clk (
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.I (fpga_clk_m2c_p[1]),
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.IB (fpga_clk_m2c_n[1]),
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.O (fpga_clk_m2c_1));
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BUFG i_rx_device_clk (
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.I (fpga_clk_m2c_1),
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.O (rx_device_clk)
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);
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IBUFDS i_ibufds_tx_device_clk (
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.I (fpga_clk_m2c_p[2]),
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.IB (fpga_clk_m2c_n[2]),
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.O (fpga_clk_m2c_2));
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BUFG i_tx_device_clk (
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.I (fpga_clk_m2c_2),
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.O (tx_device_clk)
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);
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// spi
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assign mxfe_cs = spi_csn[3:0];
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assign mxfe_mosi = {4{spi_mosi}};
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assign mxfe_sclk = {4{spi_clk}};
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assign adf4371_cs = spi_2_csn[3:0];
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assign adf4371_sclk = spi_2_clk;
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assign hmc7043_slen = spi_2_csn[4];
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assign hmc7043_sclk = spi_2_clk;
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assign pmod1_adc_sync_n = spi_3_csn[0];
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assign pmod1_adc_sdi = spi_3_mosi;
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assign pmod1_adc_sclk = spi_3_clk;
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assign spi_miso = ~spi_csn[0] ? mxfe_miso[0] :
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~spi_csn[1] ? mxfe_miso[1] :
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~spi_csn[2] ? mxfe_miso[2] :
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~spi_csn[3] ? mxfe_miso[3] :
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1'b0;
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assign spi_2_miso = |(~spi_2_csn[3:0]) ? spi_4371_miso :
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~spi_2_csn[4] ? spi_hmc_miso :
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1'b0;
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assign spi_3_miso = ~pmod1_adc_sync_n ? pmod1_adc_sdo : 1'b0;
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ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi_hmc (
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.spi_csn (spi_2_csn[4]),
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.spi_clk (spi_2_clk),
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.spi_mosi (spi_2_mosi),
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.spi_miso (spi_hmc_miso),
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.spi_sdio (hmc7043_sdata),
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.spi_dir ());
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ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi_4371 (
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.spi_csn (&spi_2_csn[3:0]),
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.spi_clk (spi_2_clk),
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.spi_mosi (spi_2_mosi),
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.spi_miso (spi_4371_miso),
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.spi_sdio (adf4371_sdio),
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.spi_dir ());
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// gpios
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ad_iobuf #(.DATA_WIDTH(1)) i_iobuf (
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.dio_t (gpio_t[32:32]),
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.dio_i (gpio_o[32:32]),
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.dio_o (gpio_i[32:32]),
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.dio_p ({hmc7043_gpio // 32
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}));
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assign hmc7043_reset = gpio_o[33];
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assign adrf5020_ctrl = gpio_o[34];
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assign hmc425a_v = gpio_o[38:35];
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assign mxfe_reset = gpio_o[44:41];
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assign mxfe_rx_en0 = gpio_o[48:45];
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assign mxfe_rx_en1 = gpio_o[52:49];
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assign mxfe_tx_en0 = gpio_o[56:53];
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assign mxfe_tx_en1 = gpio_o[60:57];
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assign dac_fifo_bypass = gpio_o[61];
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
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.dio_t (gpio_t[16:0]),
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.dio_i (gpio_o[16:0]),
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.dio_o (gpio_i[16:0]),
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.dio_p (gpio_bd));
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assign gpio_i[63:33] = gpio_o[63:33];
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assign gpio_i[31:17] = gpio_o[31:17];
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quad_mxfe_gpio_mux i_quad_mxfe_gpio_mux (
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.mxfe0_gpio(mxfe0_gpio),
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.mxfe1_gpio(mxfe1_gpio),
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.mxfe2_gpio(mxfe2_gpio),
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.mxfe3_gpio(mxfe3_gpio),
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.gpio_t(gpio_t[127:64]),
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.gpio_i(gpio_i[127:64]),
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.gpio_o(gpio_o[127:64])
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);
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assign pmod1_5045_v2 = gpio_o[120];
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assign pmod1_5045_v1 = gpio_o[121];
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assign pmod1_ctrl_ind = gpio_o[122];
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assign pmod1_ctrl_rx_combined = gpio_o[123];
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system_wrapper i_system_wrapper (
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.sys_rst (sys_rst),
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.sys_clk_clk_n (sys_clk_n),
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.sys_clk_clk_p (sys_clk_p),
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.ddr4_act_n (ddr4_act_n),
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.ddr4_adr (ddr4_addr),
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.ddr4_ba (ddr4_ba),
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.ddr4_bg (ddr4_bg),
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.ddr4_ck_c (ddr4_ck_n),
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.ddr4_ck_t (ddr4_ck_p),
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.ddr4_cke (ddr4_cke),
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.ddr4_cs_n (ddr4_cs_n),
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.ddr4_dm_n (ddr4_dm_n),
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.ddr4_dq (ddr4_dq),
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.ddr4_dqs_c (ddr4_dqs_n),
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.ddr4_dqs_t (ddr4_dqs_p),
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.ddr4_odt (ddr4_odt),
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.ddr4_reset_n (ddr4_reset_n),
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.phy_sd (1'b1),
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.phy_rst_n (phy_rst_n),
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.sgmii_rxn (phy_rx_n),
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.sgmii_rxp (phy_rx_p),
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.sgmii_txn (phy_tx_n),
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.sgmii_txp (phy_tx_p),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.sgmii_phyclk_clk_n (phy_clk_n),
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.sgmii_phyclk_clk_p (phy_clk_p),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.spi_clk_i (spi_clk),
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.spi_clk_o (spi_clk),
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.spi_csn_i (spi_csn),
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.spi_csn_o (spi_csn),
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.spi_sdi_i (spi_miso),
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.spi_sdo_i (spi_mosi),
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.spi_sdo_o (spi_mosi),
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.spi_2_clk_i (spi_2_clk),
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.spi_2_clk_o (spi_2_clk),
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.spi_2_csn_i (spi_2_csn),
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.spi_2_csn_o (spi_2_csn),
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.spi_2_sdi_i (spi_2_miso),
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.spi_2_sdo_i (spi_2_mosi),
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.spi_2_sdo_o (spi_2_mosi),
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.spi_3_clk_i (spi_3_clk),
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.spi_3_clk_o (spi_3_clk),
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.spi_3_csn_i (spi_3_csn),
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.spi_3_csn_o (spi_3_csn),
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.spi_3_sdi_i (spi_3_miso),
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.spi_3_sdo_i (spi_3_mosi),
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.spi_3_sdo_o (spi_3_mosi),
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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// FMCp
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// quad 121
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.rx_data_0_n (m2c_n[10]), // {10 15 8 4 11 9 14 13 12 3 1 2 6 0 7 5}
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.rx_data_0_p (m2c_p[10]),
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.rx_data_1_n (m2c_n[15]),
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.rx_data_1_p (m2c_p[15]),
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.rx_data_2_n (m2c_n[8]),
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.rx_data_2_p (m2c_p[8]),
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.rx_data_3_n (m2c_n[4]),
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.rx_data_3_p (m2c_p[4]),
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// quad 122
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.rx_data_4_n (m2c_n[11]),
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.rx_data_4_p (m2c_p[11]),
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.rx_data_5_n (m2c_n[9]),
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.rx_data_5_p (m2c_p[9]),
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.rx_data_6_n (m2c_n[14]),
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.rx_data_6_p (m2c_p[14]),
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.rx_data_7_n (m2c_n[13]),
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.rx_data_7_p (m2c_p[13]),
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// quad 125
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.rx_data_8_n (m2c_n[12]),
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.rx_data_8_p (m2c_p[12]),
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.rx_data_9_n (m2c_n[3]),
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.rx_data_9_p (m2c_p[3]),
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.rx_data_10_n (m2c_n[1]),
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.rx_data_10_p (m2c_p[1]),
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.rx_data_11_n (m2c_n[2]),
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.rx_data_11_p (m2c_p[2]),
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// quad 126
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.rx_data_12_n (m2c_n[6]),
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|
.rx_data_12_p (m2c_p[6]),
|
|
.rx_data_13_n (m2c_n[0]),
|
|
.rx_data_13_p (m2c_p[0]),
|
|
.rx_data_14_n (m2c_n[7]),
|
|
.rx_data_14_p (m2c_p[7]),
|
|
.rx_data_15_n (m2c_n[5]),
|
|
.rx_data_15_p (m2c_p[5]),
|
|
// quad 121
|
|
.tx_data_0_n (c2m_n[12]), // {12 14 10 4 11 9 8 3 1 2 13 15 6 0 7 5}
|
|
.tx_data_0_p (c2m_p[12]),
|
|
.tx_data_1_n (c2m_n[14]),
|
|
.tx_data_1_p (c2m_p[14]),
|
|
.tx_data_2_n (c2m_n[10]),
|
|
.tx_data_2_p (c2m_p[10]),
|
|
.tx_data_3_n (c2m_n[4]),
|
|
.tx_data_3_p (c2m_p[4]),
|
|
// quad 122
|
|
.tx_data_4_n (c2m_n[11]),
|
|
.tx_data_4_p (c2m_p[11]),
|
|
.tx_data_5_n (c2m_n[9]),
|
|
.tx_data_5_p (c2m_p[9]),
|
|
.tx_data_6_n (c2m_n[8]),
|
|
.tx_data_6_p (c2m_p[8]),
|
|
.tx_data_7_n (c2m_n[3]),
|
|
.tx_data_7_p (c2m_p[3]),
|
|
// quad 125
|
|
.tx_data_8_n (c2m_n[1]),
|
|
.tx_data_8_p (c2m_p[1]),
|
|
.tx_data_9_n (c2m_n[2]),
|
|
.tx_data_9_p (c2m_p[2]),
|
|
.tx_data_10_n (c2m_n[13]),
|
|
.tx_data_10_p (c2m_p[13]),
|
|
.tx_data_11_n (c2m_n[15]),
|
|
.tx_data_11_p (c2m_p[15]),
|
|
// quad 126
|
|
.tx_data_12_n (c2m_n[6]),
|
|
.tx_data_12_p (c2m_p[6]),
|
|
.tx_data_13_n (c2m_n[0]),
|
|
.tx_data_13_p (c2m_p[0]),
|
|
.tx_data_14_n (c2m_n[7]),
|
|
.tx_data_14_p (c2m_p[7]),
|
|
.tx_data_15_n (c2m_n[5]),
|
|
.tx_data_15_p (c2m_p[5]),
|
|
.ref_clk_q0 (ref_clk),
|
|
.ref_clk_q1 (ref_clk),
|
|
.ref_clk_q2 (ref_clk_replica),
|
|
.ref_clk_q3 (ref_clk_replica),
|
|
.rx_device_clk (rx_device_clk),
|
|
.tx_device_clk (tx_device_clk),
|
|
.rx_sync_0 (link0_rx_syncout),
|
|
.tx_sync_0 (link0_tx_syncin),
|
|
.rx_sysref_0 (sysref),
|
|
.tx_sysref_0 (sysref),
|
|
.dac_fifo_bypass (dac_fifo_bypass),
|
|
.gpio2_i (gpio_i[95:64]),
|
|
.gpio2_o (gpio_o[95:64]),
|
|
.gpio2_t (gpio_t[95:64]),
|
|
.gpio3_i (gpio_i[127:96]),
|
|
.gpio3_o (gpio_o[127:96]),
|
|
.gpio3_t (gpio_t[127:96]),
|
|
.ext_sync (sysref)
|
|
);
|
|
|
|
assign link1_rx_syncout = 4'b1111;
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|