Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project ... - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release		2016-02-19 14:09:57 +02:00
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a5gt_system_assign.tcl	a5gt: Updated ethernet clock constraints	2015-07-27 16:02:51 +03:00
a5gt_system_bd.qsys	fmcjesdadc1: Fixed project	2016-02-19 14:09:57 +02:00