zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,082 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Rejeesh Kutty 4eb28592c8 kcu105: 2015.2.1 updates 2015-08-25 09:12:32 -04:00
library util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl 2015-08-25 09:41:34 +03:00
projects kcu105: 2015.2.1 updates 2015-08-25 09:12:32 -04:00
.gitattributes Add .gitattributes file 2015-07-01 18:43:51 +02:00
.gitignore ignore xml files 2015-08-14 15:33:11 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update to Quartus 15.0. Removed release candidate note 2015-08-13 11:55:23 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.