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pluto_hdl_adi
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4e60f15e7f
pluto_hdl_adi
/
library
/
xilinx
History
Adrian Costina
a5407702bb
util_adxcvr: Don't show reset ports for disabled lanes
2018-04-11 15:09:54 +03:00
..
axi_adcfifo
axi_adcfifo_constr.xdc: Add missing backslash to command
2018-04-11 15:09:54 +03:00
axi_adxcvr
axi_*: Infer clock and reset signals of an IP
2018-04-11 15:09:54 +03:00
axi_dacfifo
axi_dacfifo: Rewrote constraints to be more specific
2018-04-11 15:09:54 +03:00
axi_xcvrlb
library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
2017-08-01 15:21:25 +02:00
common
up_clock_com: Fix the false path definitions for CDCs
2018-04-11 15:09:54 +03:00
util_adxcvr
util_adxcvr: Don't show reset ports for disabled lanes
2018-04-11 15:09:54 +03:00