d18eb85e41
The cfg_links_disable register will mask the SYNC lines, disabled links will always have a de-asserted SYNC (logic state HIGH). The FSM will stay in CGS as long as there is one active link with an asserted SYNC (logic state LOW). Update the test bench to generate the SYNC signals in different clock edges, so it can test all the possible scenarios. |
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| .. | ||
| Makefile | ||
| jesd204_tx.v | ||
| jesd204_tx_constr.sdc | ||
| jesd204_tx_constr.xdc | ||
| jesd204_tx_ctrl.v | ||
| jesd204_tx_hw.tcl | ||
| jesd204_tx_ip.tcl | ||
| jesd204_tx_lane.v | ||