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Istvan Csomortani 4b08df9ed6 ad9361/tdd: Fix generation of tx_valid_* signals 
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
 		2015-06-08 16:23:32 +03:00
library ad9361/tdd: Fix generation of tx_valid_* signals 2015-06-08 16:23:32 +03:00
projects ad9434/ad9467 : Connect reset signal for AXI streaming interface of the device dma 2015-06-04 18:09:48 +03:00
.gitignore gitignore: add non-project stuff 2015-05-01 13:17:14 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md Update README.md 2015-05-20 17:38:08 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

##NOTE

Beware! This branch is just a realease candidate. Final release expected at end of June.

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.