157afcbc33
The tb_base.v verilog files does not contain a full module definition, just some plain test code. In general the files is sourced inside the test bench main module. As is, defining a timescale in these files will generate an error, because timescale directive can not be inside a module. Delete all the timescale directive from these files. |
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| .. | ||
| tb | ||
| util_cpack2 | ||
| util_pack_common | ||
| util_upack2 | ||