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AndreiGrozav 568f2e180f ad_mul.v: Add parameters for A and B input widths 
The out width will be A + B.
This change is backward compatible and it applies to both Altera and Xilinx.
 		2018-07-18 18:19:30 +03:00
..
axi_adcfifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_adxcvr Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_dacfifo axi_dacfifo: Always use equal or not equal 2018-06-13 14:58:49 +01:00
axi_xcvrlb Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
common ad_mul.v: Add parameters for A and B input widths 2018-07-18 18:19:30 +03:00
util_adxcvr xilinx: util_adxcvr: Add support for lane polarity inversion 2018-05-02 09:37:23 +02:00