121 lines
5.0 KiB
Tcl
121 lines
5.0 KiB
Tcl
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# fmcadc4
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# adc peripherals
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ad_ip_instance axi_ad9680 axi_ad9680_core_0
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ad_ip_parameter axi_ad9680_core_0 CONFIG.ID 0
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ad_ip_instance axi_ad9680 axi_ad9680_core_1
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ad_ip_parameter axi_ad9680_core_1 CONFIG.ID 1
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ad_ip_instance axi_adxcvr axi_ad9680_xcvr
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ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 8
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ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_instance jesd204 axi_ad9680_jesd
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ad_ip_parameter axi_ad9680_jesd CONFIG.C_NODE_IS_TRANSMIT 0
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ad_ip_parameter axi_ad9680_jesd CONFIG.C_LANES 8
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ad_ip_instance axi_dmac axi_ad9680_dma
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_ip_instance util_cpack axi_ad9680_cpack
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ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64
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ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 4
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# adc common gt
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ad_ip_instance util_adxcvr util_fmcadc4_xcvr
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ad_ip_parameter util_fmcadc4_xcvr CONFIG.RX_NUM_OF_LANES 8
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ad_ip_parameter util_fmcadc4_xcvr CONFIG.TX_NUM_OF_LANES 0
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ad_ip_instance util_bsplit util_bsplit_rx_data
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ad_ip_parameter util_bsplit_rx_data CONFIG.CHANNEL_DATA_WIDTH 128
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ad_ip_parameter util_bsplit_rx_data CONFIG.NUM_OF_CHANNELS 2
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# reference clocks & resets
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create_bd_port -dir I rx_ref_clk_0
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ad_xcvrpll rx_ref_clk_0 util_fmcadc4_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_fmcadc4_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_cpll_rst_*
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# connections (gt)
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ad_xcvrcon util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd
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ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
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ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_0/rx_clk
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ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_1/rx_clk
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ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_0/rx_sof
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ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_1/rx_sof
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ad_connect axi_ad9680_jesd/rx_tdata util_bsplit_rx_data/data
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
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# connections (adc)
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ad_connect util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data
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ad_connect util_bsplit_rx_data/split_data_1 axi_ad9680_core_1/rx_data
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ad_connect axi_ad9680_core_0/adc_enable_0 axi_ad9680_cpack/adc_enable_0
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ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/adc_valid_0
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ad_connect axi_ad9680_core_0/adc_data_0 axi_ad9680_cpack/adc_data_0
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ad_connect axi_ad9680_core_0/adc_enable_1 axi_ad9680_cpack/adc_enable_1
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ad_connect axi_ad9680_core_0/adc_valid_1 axi_ad9680_cpack/adc_valid_1
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ad_connect axi_ad9680_core_0/adc_data_1 axi_ad9680_cpack/adc_data_1
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ad_connect axi_ad9680_core_1/adc_enable_0 axi_ad9680_cpack/adc_enable_2
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ad_connect axi_ad9680_core_1/adc_valid_0 axi_ad9680_cpack/adc_valid_2
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ad_connect axi_ad9680_core_1/adc_data_0 axi_ad9680_cpack/adc_data_2
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ad_connect axi_ad9680_core_1/adc_enable_1 axi_ad9680_cpack/adc_enable_3
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ad_connect axi_ad9680_core_1/adc_valid_1 axi_ad9680_cpack/adc_valid_3
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ad_connect axi_ad9680_core_1/adc_data_1 axi_ad9680_cpack/adc_data_3
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ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
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ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
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ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
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ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
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ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
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ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
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ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
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ad_connect axi_ad9680_core_0/adc_dovf axi_ad9680_fifo/adc_wovf
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ad_connect sys_cpu_clk util_fmcadc4_xcvr/up_clk
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ad_connect sys_cpu_resetn util_fmcadc4_xcvr/up_rstn
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad9680_xcvr
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ad_cpu_interconnect 0x44A00000 axi_ad9680_core_0
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ad_cpu_interconnect 0x44A10000 axi_ad9680_core_1
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ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
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# interconnect (mem/adc)
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
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