Adrian Costina 3436210429 axi_adcfifo: Infer clock and reset signals		2018-04-11 15:09:54 +03:00
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Makefile	Regenerate library Makefiles using the new shared Makefile include	2018-04-11 15:09:54 +03:00
axi_adcfifo.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_adcfifo_adc.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_adcfifo_constr.xdc	axi_adcfifo_constr.xdc: Add missing backslash to command	2018-04-11 15:09:54 +03:00
axi_adcfifo_dma.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_adcfifo_ip.tcl	axi_adcfifo: Infer clock and reset signals	2018-04-11 15:09:54 +03:00
axi_adcfifo_rd.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
axi_adcfifo_wr.v	util_axis_fifo: instantiate block ram in async mode	2018-04-11 15:09:54 +03:00