Istvan Csomortani 79b6ba29ce all: Rename altera to intel		2019-06-29 06:53:51 +03:00
..
Makefile	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
axi_adrv9009.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
axi_adrv9009_hw.tcl	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
axi_adrv9009_if.v	axi_adrv9009: Use the correct clock for the observation path interface	2018-07-09 12:41:52 +01:00
axi_adrv9009_ip.tcl	library: Update scripts/adi_ad_ip.tcl and IPs	2019-04-09 16:07:14 +03:00
axi_adrv9009_rx.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
axi_adrv9009_rx_channel.v	axi_adrv9009: Split DATAPATH parameter in multiple parameters. Map the parameters in the CONFIG register	2018-06-29 11:10:39 +03:00
axi_adrv9009_rx_os.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
axi_adrv9009_tx.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
axi_adrv9009_tx_channel.v	axi_adrv9009: Updates for ad_dds phase acc wrapper	2018-07-18 18:19:30 +03:00