3e7325b29a
The minimum decimation rate of the CIC block is five, this means data arrives at the FIR filter at most every five clock cycles. The decimation rate of the filter is two so the filter produces an output at most every ten clock cycles. This allows for ten clock cycles to compute the result. The current implementation of the filter uses a fully pipelined architecture with one multiplier for each coefficient. Which then do work for one clock cycle and sit idle for the next nine clock cycles. Rework the filter to be sequential reducing the number of required multipliers to one. In addition exploit the symmetric structure of the filter to make use of the preadder reducing the required multiply operations by two. This significantly reduces the logic utilization of the filter as well as moderately reduces power consumption. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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