zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library
History
Lars-Peter Clausen 3d5ef9a8ed util_dac_unpack: Fix unpack order with 1 channel 
Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.

This fixes issues with the unpack order when only one channel is active.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2014-10-10 16:26:14 +03:00
..
axi_ad9122 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
axi_ad9144 library: remove all constraints for now 2014-10-07 16:59:19 -04:00
axi_ad9152 daq3: vivado build 2014-10-06 10:34:02 -04:00
axi_ad9234 library: remove all constraints for now 2014-10-07 16:59:19 -04:00
axi_ad9250 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
axi_ad9265 axi_ad9265: Updated project with new up independent read/write 2014-10-03 12:32:08 +03:00
axi_ad9361 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
axi_ad9434 axi_ad9434: Independent read/write update 2014-10-07 18:01:44 +03:00
axi_ad9467 axi_ad9467: Independent read/write update 2014-10-08 11:23:44 +03:00
axi_ad9625 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
axi_ad9643 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
axi_ad9652 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
axi_ad9671 axi_ad9671: altera axi4lite changes 2014-10-09 15:25:07 -04:00
axi_ad9680 library: remove all constraints for now 2014-10-07 16:59:19 -04:00
axi_clkgen up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
axi_dmac axi_dmac: Add default driver values for optional input ports 2014-10-10 16:25:46 +03:00
axi_fifo axi_dmac/axi_fifo: Add missing file 2014-09-15 21:04:57 +02:00
axi_fifo2s Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
axi_hdmi_tx library: remove all constraints for now 2014-10-07 16:59:19 -04:00
axi_i2s_adi axi_i2s: Add missing signals to the regmap read process sensitivity list 2014-10-10 16:25:56 +03:00
axi_jesd_gt library: remove all constraints for now 2014-10-07 16:59:19 -04:00
axi_mc_controller Remove BASEADDR/HIGHADDR parameters 2014-09-11 12:26:37 +02:00
axi_mc_current_monitor Remove BASEADDR/HIGHADDR parameters 2014-09-11 12:26:37 +02:00
axi_mc_speed Remove BASEADDR/HIGHADDR parameters 2014-09-11 12:26:37 +02:00
axi_spdif_tx axi_spdif: Add missing signals to the regmap read sensitifity list 2014-10-10 16:26:09 +03:00
common up_axi: altera can not handle same clock assertion of arready and rvalid 2014-10-09 15:25:05 -04:00
controllerperipheralhdladi_pcore motor_control: Updated the FOC IP 2014-09-08 15:52:18 +03:00
ip_pid_controller Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
prcfg prcfg: Update the prcfg logic to the new ad9361 interface 2014-08-05 17:54:37 +03:00
scripts scripts/adi_ip: Add helper function to create bus clock and reset interface 2014-10-10 16:11:31 +03:00
util_adc_pack util_adc_pack: Hide unused signals 2014-10-10 16:20:29 +03:00
util_dac_unpack util_dac_unpack: Fix unpack order with 1 channel 2014-10-10 16:26:14 +03:00
util_i2c_mixer pointers to directories 2014-02-28 16:58:30 -05:00
util_rfifo fifo- monitor status signals 2014-06-25 12:15:13 -04:00
util_sync_reset util_sync_reset: Fix polarity of the sync_resetn signal 2014-03-25 13:03:12 +01:00
util_wfifo fifo- monitor status signals 2014-06-25 12:15:13 -04:00