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Lars-Peter Clausen 3d5ef9a8ed util_dac_unpack: Fix unpack order with 1 channel 
Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.

This fixes issues with the unpack order when only one channel is active.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2014-10-10 16:26:14 +03:00
library util_dac_unpack: Fix unpack order with 1 channel 2014-10-10 16:26:14 +03:00
projects fmcomms2: Connect DMA directly to the HP ports 2014-10-10 16:25:14 +03:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga