Istvan Csomortani 6bbf1ae83c avl_dacfifo: End of burst is not always end of a transaction ... The XFER_END state defines the end of a transaction, when the entire data set is written or read to/from the DDRx memory. A transaction can contain multiple Avalon bursts. Make sure that the FSM goes back into staging phase at the end of each burst; also define a signals which indicate the end of each burst for control.		2017-12-09 09:56:33 +00:00
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avl_dacfifo.v	avl_dacfifo: Refactor the fifo	2017-10-31 14:30:06 +00:00
avl_dacfifo_byteenable_coder.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
avl_dacfifo_byteenable_decoder.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
avl_dacfifo_constr.sdc	avl_dacfifo: Refactor the fifo	2017-10-31 14:30:06 +00:00
avl_dacfifo_hw.tcl	avl_dacfifo: Refactor the fifo	2017-10-31 14:30:06 +00:00
avl_dacfifo_rd.v	avl_dacfifo: End of burst is not always end of a transaction	2017-12-09 09:56:33 +00:00
avl_dacfifo_wr.v	avl_dacfifo: Fix write enable generation	2017-11-01 12:22:18 +00:00
util_dacfifo_bypass.v	avl_dacfifo: Refactor the fifo	2017-10-31 14:30:06 +00:00