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Lars-Peter Clausen 5f83e20d33 m2k: standalone: Rework PS7 clocking 
At the moment the PS7 is using three PLLs to generate its clocking tree.
One for the DDR, one for the ARM and one for the IO. This allows to run all
components at their respective maximum clock and extract maximum
performance from all components.

With some slight modifications it is possible to trade maximum performance
for a reduction in power consumption by using the same PLL for all three
sets of components and disabling the other two PLLs.

The CPU is now running at 500MHz rather than 666MHz and the DDR memory at
500MHz rather than 533MHz. This reduces power consumption by ~125mW.

This is OK since neither of them is a bottleneck for overall system
performance.

In addition software will downclock the CPU to 250MHz when full performance
is not required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-04-18 12:17:40 +02:00
..
ad6676evb all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad7616_sdz all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad7768evb all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad9265_fmc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad9434_fmc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad9467_fmc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad9739a_fmc all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
adrv9371x Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
adv7511 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
arradio Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
cftl_cip cftl_cip: cleaned up some warnings 2017-04-18 10:29:20 +03:00
cftl_std cftl_std: cleaned up some warnings 2017-04-18 10:32:28 +03:00
cn0363 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
common kcu105: ip automatic version update 2017-04-18 11:59:54 +03:00
daq1 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
daq2 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
daq3 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
fmcadc2 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcadc4 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcadc5 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcjesdadc1 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
fmcomms2 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
fmcomms5 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcomms7 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
fmcomms11 make updates 2017-03-20 16:05:18 -04:00
imageon imageon: ip automatic version update 2017-04-14 16:54:42 +03:00
m2k m2k: standalone: Rework PS7 clocking 2017-04-18 12:17:40 +02:00
motcon2_fmc motcon2_fmc: cleaned up some warnings 2017-04-18 10:33:13 +03:00
pluto pluto: cleaned up some warnings 2017-04-18 10:34:13 +03:00
pzsdr1 make updates 2017-03-20 16:05:18 -04:00
pzsdr2 make updates 2017-03-20 16:05:18 -04:00
scripts scripts: Created ADI_POWER_OPTIMIZATION parameter for enabling power optimizations in the implementation stage 2017-04-18 12:17:40 +02:00
usb_fx3 usb_fx3: ip automatic version update 2017-04-14 16:55:30 +03:00
usdrx1 Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
usrpe31x make updates 2017-03-20 16:05:18 -04:00
Makefile Make: Update Makefiles 2017-02-10 16:32:58 +02:00