Lars-Peter Clausen a0e30a2211 util_axis_fifo: Improve clock gating of registers and BRAM ... Currently the BRAM and data registers in the util_axis_data are ungated when the FIFO is ready to receive data. This good for high-performance since it reduces the number of control signals. But it is bad from a power point of view since it causes additional reads and writes. Change the core gate the BRAM and data register if either the consumer is not ready to accept data or the producer has no data to offer. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-04-18 12:17:39 +02:00
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Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
address_gray.v	all: Change tab to double space	2016-10-01 18:13:42 +03:00
address_gray_pipelined.v	all: Change tab to double space	2016-10-01 18:13:42 +03:00
address_sync.v	all: Change tab to double space	2016-10-01 18:13:42 +03:00
util_axis_fifo.v	util_axis_fifo: Improve clock gating of registers and BRAM	2017-04-18 12:17:39 +02:00
util_axis_fifo_ip.tcl	util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl	2015-08-25 09:41:34 +03:00