8dc2161870
In its default configuration the ram_2port module as a read latency of 2 clock cycles. Both the read address as well as the output data are registered. This is not the behavior that is expected from the alt_mem_asym module and causes incorrect behavior and data corruption in the util_adc_fifo. Disable the data output register to get a read latency of 1 clock cycle. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| alt_ifconv | ||
| alt_mem_asym | ||
| alt_mul | ||
| alt_serdes | ||
| ad_dcfilter.v | ||
| ad_mem_asym.v | ||
| ad_mul.v | ||
| up_clock_mon_constr.sdc | ||
| up_rst_constr.sdc | ||
| up_xfer_cntrl_constr.sdc | ||
| up_xfer_status_constr.sdc | ||