Lars-Peter Clausen e4bb2beaf1 altera: adi_jesd204: Export link domain reset ... Export the reset signal for the link clock domain. This can be used by external logic that is in the link clock domain to reset itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-08-24 17:43:12 +02:00
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adi_jesd204	altera: adi_jesd204: Export link domain reset	2017-08-24 17:43:12 +02:00
avl_adxcfg	avl_adxcfg: Consistently use non-blocking assignments	2017-07-24 16:06:00 +02:00
avl_adxcvr	avl_adxcvr: Perform octet order swap	2017-08-03 17:57:58 +02:00
avl_adxcvr_octet_swap	avl_adxcvr: Perform octet order swap	2017-08-03 17:57:58 +02:00
avl_adxphy	avl_adxcvr: Simplify TX lane mapping	2017-08-03 17:57:58 +02:00
avl_dacfifo	avl_dacfifo: Update IP to qsys flow	2017-08-22 09:16:21 +01:00
axi_adxcvr	axi_adxcvr: Avoid implicit signal truncation warning	2017-08-07 17:42:17 +02:00
common	alt_mem_asym: Set read latency to 1 clock cycle	2017-08-13 10:28:11 +02:00
jesd204_phy	altera: jesd204_phy: Fix indention issues	2017-08-21 13:57:55 +02:00