66 lines
1.9 KiB
Verilog
66 lines
1.9 KiB
Verilog
// -------------------------------------------------------------
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//
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// File Name: hdlsrc\qpskhdltest\QPSK_Modulator.v
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// Created: 2014-04-21 15:30:34
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//
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// Generated by MATLAB 8.2 and HDL Coder 3.3
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//
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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//
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// Module: QPSK_Modulator
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// Source Path: qpskhdltest/QPSK Modulator
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// Hierarchy Level: 0
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//
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module QPSK_Modulator
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(
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in0,
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out0_re,
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out0_im
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);
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input [1:0] in0; // ufix2
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output signed [15:0] out0_re; // sfix16_En15
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output signed [15:0] out0_im; // sfix16_En15
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parameter signed [15:0] t1_re_0 = 23170; // sfix16
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parameter signed [15:0] t1_re_1 = -23170; // sfix16
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parameter signed [15:0] t1_re_2 = -23170; // sfix16
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parameter signed [15:0] t1_re_3 = 23170; // sfix16
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parameter signed [15:0] t1_im_0 = 23170; // sfix16
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parameter signed [15:0] t1_im_1 = 23170; // sfix16
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parameter signed [15:0] t1_im_2 = -23170; // sfix16
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parameter signed [15:0] t1_im_3 = -23170; // sfix16
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wire [1:0] constellationLUTaddress; // ufix2
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wire signed [15:0] constellationLUT_t1_re [0:3]; // sfix16_En15 [4]
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wire signed [15:0] constellationLUT_t1_im [0:3]; // sfix16_En15 [4]
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assign constellationLUTaddress = in0;
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assign constellationLUT_t1_re[0] = t1_re_0;
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assign constellationLUT_t1_re[1] = t1_re_1;
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assign constellationLUT_t1_re[2] = t1_re_2;
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assign constellationLUT_t1_re[3] = t1_re_3;
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assign constellationLUT_t1_im[0] = t1_im_0;
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assign constellationLUT_t1_im[1] = t1_im_1;
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assign constellationLUT_t1_im[2] = t1_im_2;
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assign constellationLUT_t1_im[3] = t1_im_3;
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assign out0_re = constellationLUT_t1_re[constellationLUTaddress];
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assign out0_im = constellationLUT_t1_im[constellationLUTaddress];
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endmodule // QPSK_Modulator
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