57 lines
2.1 KiB
Verilog
57 lines
2.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_fir_dec (
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input aclk,
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input s_axis_data_tvalid,
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output s_axis_data_tready,
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input [15:0] channel_0,
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input [15:0] channel_1,
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input decimate,
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output m_axis_data_tvalid,
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output [31:0] m_axis_data_tdata);
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wire [31:0] s_axis_data_tdata;
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wire m_axis_data_tvalid_s;
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wire [31:0] m_axis_data_tdata_s;
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assign s_axis_data_tdata = {channel_1, channel_0};
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assign m_axis_data_tvalid = (decimate == 1'b1) ? m_axis_data_tvalid_s : s_axis_data_tvalid;
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assign m_axis_data_tdata = (decimate == 1'b1) ? {m_axis_data_tdata_s[30:16], 1'b0, m_axis_data_tdata_s[14:0], 1'b0} : {channel_1, channel_0};
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fir_decim decimator (
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.aclk(aclk),
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.s_axis_data_tvalid(s_axis_data_tvalid),
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.s_axis_data_tready(s_axis_data_tready),
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.s_axis_data_tdata(s_axis_data_tdata),
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.m_axis_data_tvalid(m_axis_data_tvalid_s),
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.m_axis_data_tdata(m_axis_data_tdata_s)
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);
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endmodule // util_fir_dec
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