117 lines
3.6 KiB
Verilog
117 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_xfer_status #(
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parameter DATA_WIDTH = 8) (
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// up interface
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input up_rstn,
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input up_clk,
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output reg [DW:0] up_data_status,
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// device interface
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input d_rst,
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input d_clk,
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input [DW:0] d_data_status);
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localparam DW = DATA_WIDTH - 1;
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// internal registers
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reg d_xfer_state_m1 = 'd0;
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reg d_xfer_state_m2 = 'd0;
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reg d_xfer_state = 'd0;
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reg [ 5:0] d_xfer_count = 'd0;
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reg d_xfer_toggle = 'd0;
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reg [DW:0] d_xfer_data = 'd0;
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reg [DW:0] d_acc_data = 'd0;
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reg up_xfer_toggle_m1 = 'd0;
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reg up_xfer_toggle_m2 = 'd0;
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reg up_xfer_toggle_m3 = 'd0;
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reg up_xfer_toggle = 'd0;
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// internal signals
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wire d_xfer_enable_s;
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wire up_xfer_toggle_s;
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// device status transfer
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assign d_xfer_enable_s = d_xfer_state ^ d_xfer_toggle;
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always @(posedge d_clk or posedge d_rst) begin
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if (d_rst == 1'b1) begin
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d_xfer_state_m1 <= 'd0;
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d_xfer_state_m2 <= 'd0;
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d_xfer_state <= 'd0;
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d_xfer_count <= 'd0;
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d_xfer_toggle <= 'd0;
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d_xfer_data <= 'd0;
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d_acc_data <= 'd0;
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end else begin
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d_xfer_state_m1 <= up_xfer_toggle;
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d_xfer_state_m2 <= d_xfer_state_m1;
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d_xfer_state <= d_xfer_state_m2;
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d_xfer_count <= d_xfer_count + 1'd1;
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if ((d_xfer_count == 6'd1) && (d_xfer_enable_s == 1'b0)) begin
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d_xfer_toggle <= ~d_xfer_toggle;
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d_xfer_data <= d_acc_data;
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end
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if ((d_xfer_count == 6'd1) && (d_xfer_enable_s == 1'b0)) begin
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d_acc_data <= d_data_status;
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end else begin
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d_acc_data <= d_acc_data | d_data_status;
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end
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end
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end
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assign up_xfer_toggle_s = up_xfer_toggle_m3 ^ up_xfer_toggle_m2;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_xfer_toggle_m1 <= 'd0;
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up_xfer_toggle_m2 <= 'd0;
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up_xfer_toggle_m3 <= 'd0;
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up_xfer_toggle <= 'd0;
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up_data_status <= 'd0;
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end else begin
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up_xfer_toggle_m1 <= d_xfer_toggle;
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up_xfer_toggle_m2 <= up_xfer_toggle_m1;
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up_xfer_toggle_m3 <= up_xfer_toggle_m2;
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up_xfer_toggle <= up_xfer_toggle_m3;
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if (up_xfer_toggle_s == 1'b1) begin
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up_data_status <= d_xfer_data;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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