69 lines
2.3 KiB
Verilog
69 lines
2.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns / 1ps
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module debouncer
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//----------- Paramters Declarations -------------------------------------------
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#(
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parameter DEBOUNCER_LENGTH = 4
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)
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//----------- Ports Declarations -----------------------------------------------
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(
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input clk_i,
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input rst_i,
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input sig_i,
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output reg sig_o
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [DEBOUNCER_LENGTH-1:0] shift_reg;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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always @(posedge clk_i)
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begin
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if(rst_i == 1)
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begin
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shift_reg <= 0;
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sig_o <= 0;
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end
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else
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begin
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shift_reg <= {shift_reg[DEBOUNCER_LENGTH-2:0], sig_i};
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if(shift_reg == {DEBOUNCER_LENGTH{1'b1}})
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begin
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sig_o <= 1'b1;
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end
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else if(shift_reg == {DEBOUNCER_LENGTH{1'b0}})
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begin
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sig_o <= 1'b0;
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end
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end
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end
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endmodule
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