83 lines
2.1 KiB
Verilog
83 lines
2.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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module dmac_response_handler (
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input clk,
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input resetn,
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input bvalid,
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output bready,
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input [1:0] bresp,
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output reg [ID_WIDTH-1:0] id,
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input [ID_WIDTH-1:0] request_id,
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input sync_id,
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input enable,
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output reg enabled,
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input eot,
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output resp_valid,
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input resp_ready,
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output resp_eot,
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output [1:0] resp_resp
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);
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parameter ID_WIDTH = 3;
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`include "resp.h"
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`include "inc_id.h"
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assign resp_resp = bresp;
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assign resp_eot = eot;
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wire active = id != request_id && enabled;
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assign bready = active && resp_ready;
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assign resp_valid = active && bvalid;
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// We have to wait for all responses before we can disable the response handler
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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enabled <= 1'b0;
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end else begin
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if (enable)
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enabled <= 1'b1;
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else if (request_id == id)
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enabled <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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id <= 'h0;
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end else begin
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if ((bready && bvalid) ||
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(sync_id && id != request_id))
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id <= inc_id(id);
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end
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end
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endmodule
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