pluto_hdl_adi/library/altera
Istvan Csomortani 960883c789 avl_dacfifo: Fix dac_xfer_req generation
The dac_xfer_req should indicate one single thing, that the FIFO is in
read phase. Should not be affected by any signals, which indicates data
validity on any interface. (e.g. dac_valid)
This signal is not used by the device core, its main purpose is to
indicate the state of the interface for a posible intermediat processing
module.
2017-11-03 09:32:10 +00:00
..
adi_jesd204 jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps 2017-10-25 14:36:54 +01:00
avl_adxcfg avl_adxcfg: Consistently use non-blocking assignments 2017-07-24 16:06:00 +02:00
avl_adxcvr avl_adxcvr: Perform octet order swap 2017-08-03 17:57:58 +02:00
avl_adxcvr_octet_swap avl_adxcvr: Perform octet order swap 2017-08-03 17:57:58 +02:00
avl_adxphy avl_adxcvr: Simplify TX lane mapping 2017-08-03 17:57:58 +02:00
avl_dacfifo avl_dacfifo: Fix dac_xfer_req generation 2017-11-03 09:32:10 +00:00
axi_adxcvr axi_adxcvr: Avoid implicit signal truncation warning 2017-08-07 17:42:17 +02:00
common altera/ad_mem_asym: Delete it, QSYS flow is used 2017-09-25 08:57:26 +01:00
jesd204_phy jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps 2017-10-25 14:36:54 +01:00