Rejeesh Kutty 72431ff952 a10soc: Connect AXI register reset		2018-04-11 15:09:54 +03:00
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a10soc_plddr4_assign.tcl	a10soc/plddr4- differential refclk	2017-03-06 14:11:36 -05:00
a10soc_plddr4_dacfifo_qsys.tcl	avl_dacfifo: Refactor the fifo	2017-10-31 14:30:06 +00:00
a10soc_system_assign.tcl	common: a10soc: Use correct DDR memory reference clock type	2017-08-07 17:42:17 +02:00
a10soc_system_qsys.tcl	a10soc: Connect AXI register reset	2018-04-11 15:09:54 +03:00