pluto_hdl_adi/library
Laszlo Nagy bfc8ec28c3 util_axis_fifo: instantiate block ram in async mode
In cases when a shallow FIFO is requested the synthesizer infers distributed RAM
instead of block RAMs. This can be an issue when the clocks of the FIFO are
asynchronous since a timing path is created though the LUTs which implement the
memory, resulting in timing failures. Ignoring timing through the path is not a
solution since would lead to metastability.
This does not happens with block RAMs.

The solution is to use the ad_mem (block RAM) in case of async clocks and letting
the synthesizer do it's job in case of sync clocks for optimal resource utilization.
2018-04-11 15:09:54 +03:00
..
altera util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
axi_ad5766 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad6676 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad7616 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9122 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9144 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9152 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9162 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9250 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9265 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9361 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9371 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9379 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9434 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9467 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9625 util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
axi_ad9671 util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
axi_ad9680 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9684 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9739a license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_ad9963 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_adc_decimate license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_adc_trigger license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_clkgen license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_dac_interpolate license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_dmac license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_fmcadc5_sync license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_generic_adc license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_gpreg license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_hdmi_rx license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_hdmi_tx util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
axi_i2s_adi license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_intr_monitor license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_logic_analyzer license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_mc_controller license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_mc_current_monitor license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_mc_speed license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_rd_wr_combiner license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_spdif_rx license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_spdif_tx license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
axi_usb_fx3 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
cn0363 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
common util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
cordic_demod license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
interfaces interface: Update the transceiver interfaces 2017-09-25 18:02:04 +01:00
jesd204 axi_*: Infer clock and reset signals of an IP 2018-04-11 15:09:54 +03:00
prcfg license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
scripts scripts:adi_ip: Update web address format 2018-04-11 15:09:54 +03:00
spi_engine license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_adcfifo license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_axis_fifo util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
util_axis_resize license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_axis_upscale util_axis_upscale: Initial commit 2018-04-11 15:09:54 +03:00
util_bsplit license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_cdc license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_cic license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_clkdiv license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_cpack license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_dacfifo util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
util_delay util_delay: Initial commit 2017-05-25 15:12:10 +03:00
util_extract license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_fir_dec license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_fir_int license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_gmii_to_rgmii license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_i2c_mixer license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_mfifo util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
util_pulse_gen util_pulse_gen: Add Makefile 2017-04-27 11:28:25 +03:00
util_rfifo util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
util_sigma_delta_spi license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_tdd_sync license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_upack license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_var_fifo license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
util_wfifo util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
xilinx util_axis_fifo: instantiate block ram in async mode 2018-04-11 15:09:54 +03:00
Makefile util_axis_upscale: Initial commit 2018-04-11 15:09:54 +03:00