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Qsys allows to query to query the clock domain that is associated with a clock input of a peripheral. This allows to automatically detect whether the different clocks of the DMAC are asynchronous and CDC logic needs to be inserted or not. Auto-detection has the advantages that the configuration parameters don't need to be set manually and the optional configuration will be choose automatically. There is also less chance of error of leaving the settings in a wrong configuration when e.g. the clock domains change. In case the auto-detection should ever fail configuration options that provide a manual overwrite are added as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
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