35988b2dba
Currently the hdmi_de_int signal is asserted one clock cycle too early in packed 422 mode. As a result the EAV sequence ends up in the first pixel and every other pixel is off by one. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
#HDL Reference Designs
Analog Devices HDL libraries and projects
##NOTE
Beware! This branch is just a realease candidate. Final release expected at end of June.
###Tools version:
- Xilinx : Vivado 2014.4.1
- Altera : Quartus 14.1
###Documentation and support
For first time users, it is highly recommended to go through our HDL user guide.
For support please visit our FPGA Reference Designs Support Community on EngineerZone.