280 lines
9.0 KiB
Verilog
280 lines
9.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2016(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dacfifo_dac (
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axi_clk,
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axi_dvalid,
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axi_ddata,
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axi_dready,
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axi_xfer_req,
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dac_clk,
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dac_valid,
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dac_data,
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dac_xfer_out,
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dac_dunf,
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dac_dovf
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);
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// parameters
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parameter AXI_DATA_WIDTH = 512;
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parameter DAC_DATA_WIDTH = 64;
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localparam MEM_RATIO = AXI_DATA_WIDTH/DAC_DATA_WIDTH;
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localparam DAC_ADDRESS_WIDTH = 8;
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localparam AXI_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
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(MEM_RATIO == 2) ? (DAC_ADDRESS_WIDTH - 1) :
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(MEM_RATIO == 4) ? (DAC_ADDRESS_WIDTH - 2) :
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(DAC_ADDRESS_WIDTH - 3);
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localparam BUF_THRESHOLD_LO = 8'd32;
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localparam BUF_THRESHOLD_HI = 8'd240;
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// dma write
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input axi_clk;
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input axi_dvalid;
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input [(AXI_DATA_WIDTH-1):0] axi_ddata;
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output axi_dready;
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input axi_xfer_req;
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// dac read
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input dac_clk;
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input dac_valid;
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output [(DAC_DATA_WIDTH-1):0] dac_data;
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output dac_xfer_out;
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output dac_dunf;
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output dac_dovf;
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// internal registers
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reg [(AXI_ADDRESS_WIDTH-1):0] axi_waddr = 'd0;
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reg [(DAC_ADDRESS_WIDTH-1):0] axi_waddr_g = 'd0;
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reg [(DAC_ADDRESS_WIDTH-1):0] axi_raddr = 'd0;
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reg [(DAC_ADDRESS_WIDTH-1):0] axi_raddr_m = 'd0;
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reg [(DAC_ADDRESS_WIDTH-1):0] axi_addr_diff = 'd0;
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reg axi_dready = 'd0;
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reg axi_almost_full = 1'b0;
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reg axi_dwunf = 1'b0;
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reg axi_almost_empty = 1'b0;
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reg axi_dwovf = 1'b0;
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reg dac_rst = 'd0;
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reg dac_rd = 'd0;
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reg dac_rd_d = 'd0;
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reg [(DAC_DATA_WIDTH-1):0] dac_rdata_d = 'd0;
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reg [(DAC_ADDRESS_WIDTH-1):0] dac_raddr = 'd0;
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reg [(DAC_ADDRESS_WIDTH-1):0] dac_raddr_g = 'd0;
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reg [ 2:0] dac_dunf_m = 3'b0;
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reg [ 2:0] dac_dovf_m = 3'b0;
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reg [ 2:0] dac_xfer_req_m = 3'b0;
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// internal signals
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wire [DAC_ADDRESS_WIDTH:0] axi_addr_diff_s;
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wire [(DAC_ADDRESS_WIDTH-1):0] axi_waddr_s;
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wire dac_wready_s;
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wire dac_rd_s;
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wire [(DAC_DATA_WIDTH-1):0] dac_rdata_s;
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wire dac_valid_s;
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// binary to grey conversion
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function [7:0] b2g;
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input [7:0] b;
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reg [7:0] g;
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begin
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g[7] = b[7];
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g[6] = b[7] ^ b[6];
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g[5] = b[6] ^ b[5];
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g[4] = b[5] ^ b[4];
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g[3] = b[4] ^ b[3];
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g[2] = b[3] ^ b[2];
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g[1] = b[2] ^ b[1];
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g[0] = b[1] ^ b[0];
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b2g = g;
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end
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endfunction
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// grey to binary conversion
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function [7:0] g2b;
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input [7:0] g;
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reg [7:0] b;
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begin
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b[7] = g[7];
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b[6] = b[7] ^ g[6];
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b[5] = b[6] ^ g[5];
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b[4] = b[5] ^ g[4];
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b[3] = b[4] ^ g[3];
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b[2] = b[3] ^ g[2];
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b[1] = b[2] ^ g[1];
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b[0] = b[1] ^ g[0];
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g2b = b;
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end
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endfunction
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// write interface
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always @(posedge axi_clk) begin
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if (axi_xfer_req == 1'b0) begin
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axi_waddr <= 'd0;
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axi_waddr_g <= 'd0;
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end else begin
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if (axi_dvalid == 1'b1) begin
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axi_waddr <= axi_waddr + 1'b1;
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end
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axi_waddr_g <= b2g(axi_waddr_s);
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end
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end
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// underflow / overflow
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assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr;
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assign axi_waddr_s = (MEM_RATIO == 1) ? axi_waddr :
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(MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
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(MEM_RATIO == 4) ? {axi_waddr, 2'd0} :
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{axi_waddr, 3'd0};
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always @(posedge axi_clk) begin
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if (axi_xfer_req == 1'b0) begin
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axi_addr_diff <= 'd0;
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axi_raddr <= 'd0;
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axi_raddr_m <= 'd0;
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axi_dready <= 'd0;
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axi_almost_full <= 1'b0;
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axi_dwunf <= 1'b0;
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axi_almost_empty <= 1'b0;
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axi_dwovf <= 1'b0;
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end else begin
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axi_raddr_m <= g2b(dac_raddr_g);
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axi_raddr <= axi_raddr_m;
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axi_addr_diff <= axi_addr_diff_s[DAC_ADDRESS_WIDTH-1:0];
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if (axi_addr_diff >= BUF_THRESHOLD_HI) begin
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axi_dready <= 1'b0;
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end else if (axi_addr_diff <= BUF_THRESHOLD_LO) begin
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axi_dready <= 1'b1;
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end
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if (axi_addr_diff > BUF_THRESHOLD_HI) begin
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axi_almost_full <= 1'b1;
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end else begin
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axi_almost_full <= 1'b0;
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end
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if (axi_addr_diff < BUF_THRESHOLD_LO) begin
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axi_almost_empty <= 1'b1;
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end else begin
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axi_almost_empty <= 1'b0;
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end
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axi_dwunf <= (axi_addr_diff == 0) ? 1'b1 : 1'b0;
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axi_dwovf <= (axi_addr_diff == {(DAC_ADDRESS_WIDTH){1'b1}}) ? 1'b1 : 1'b0;
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end
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end
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always @(posedge dac_clk) begin
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dac_dunf_m <= {dac_dunf_m[1:0], axi_dwunf};
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dac_dovf_m <= {dac_dovf_m[1:0], axi_dwovf};
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dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
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end
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assign dac_dovf = dac_dovf_m[2];
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assign dac_dunf = dac_dunf_m[2];
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assign dac_xfer_out = dac_xfer_req_m[2];
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// read interface
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assign dac_rd_s = dac_xfer_out & dac_valid;
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always @(posedge dac_clk) begin
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if (dac_xfer_out == 1'b0) begin
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dac_rd <= 'd0;
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dac_rd_d <= 'd0;
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dac_rdata_d <= 'd0;
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dac_raddr <= 'd0;
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dac_raddr_g <= 'd0;
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end else begin
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dac_rd <= dac_rd_s;
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dac_rd_d <= dac_rd;
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dac_rdata_d <= dac_rdata_s;
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if (dac_rd_s == 1'b1) begin
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dac_raddr <= dac_raddr + 1'b1;
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end
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dac_raddr_g <= b2g(dac_raddr);
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end
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end
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// instantiations
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH),
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.A_DATA_WIDTH (AXI_DATA_WIDTH),
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.B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH),
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.B_DATA_WIDTH (DAC_DATA_WIDTH))
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i_mem_asym (
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.clka (axi_clk),
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.wea (axi_dvalid),
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.addra (axi_waddr),
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.dina (axi_ddata),
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.clkb (dac_clk),
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.addrb (dac_raddr),
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.doutb (dac_rdata_s));
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ad_axis_inf_rx #(.DATA_WIDTH(DAC_DATA_WIDTH)) i_axis_inf (
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.clk (dac_clk),
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.rst (dac_rst),
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.valid (dac_rd_d),
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.last (1'd0),
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.data (dac_rdata_d),
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.inf_valid (dac_valid_s),
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.inf_last (),
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.inf_data (dac_data),
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.inf_ready (dac_valid));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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