pluto_hdl_adi/library/axi_dmac/tb
Lars-Peter Clausen 764f31463e axi_dmac: tb: Allow testing asymmetric interface widths
One of the major features of the DMAC is being able to handle non matching
interface widths for the destination and source side.

Currently the test benches only support the case where the width for the
source and the destination side are the same. Extend them so that it is
possible to also test and verify setups where the width is not the same.

To accomplish this each byte memory location is treated as if it contained
the lower 8 bytes of its address. And then the written/read data is
compared to the expected data based on that.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-30 23:41:49 +02:00
..
axi_read_slave.v axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
axi_slave.v axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
axi_write_slave.v axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
dma_read_shutdown_tb axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
dma_read_shutdown_tb.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
dma_read_tb axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
dma_read_tb.v axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
dma_write_shutdown_tb axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
dma_write_shutdown_tb.v axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
dma_write_tb axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
dma_write_tb.v axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
regmap_tb axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
regmap_tb.v axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
reset_manager_tb axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
reset_manager_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
run_tb.sh axi_dmac/tb: Add support for xsim 2018-11-07 12:13:06 +02:00
tb_base.v axi_dmac: Add simple register map testbench 2018-05-03 14:49:06 +02:00