107 lines
3.9 KiB
Verilog
107 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// PN monitors
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`timescale 1ns/100ps
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module ad_pnmon #(
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parameter DATA_WIDTH = 16) (
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// adc interface
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input adc_clk,
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input adc_valid_in,
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input [(DATA_WIDTH-1):0] adc_data_in,
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input [(DATA_WIDTH-1):0] adc_data_pn,
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// pn out of sync and error
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output adc_pn_oos,
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output adc_pn_err);
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// internal registers
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reg adc_valid_d = 'd0;
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reg adc_pn_match_d = 'd0;
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reg adc_pn_match_z = 'd0;
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reg adc_pn_oos_int = 'd0;
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reg adc_pn_err_int = 'd0;
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reg [ 3:0] adc_pn_oos_count = 'd0;
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// internal signals
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wire adc_pn_match_d_s;
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wire adc_pn_match_z_s;
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wire adc_pn_match_s;
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wire adc_pn_update_s;
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wire adc_pn_err_s;
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// make sure data is not 0, sequence will fail.
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assign adc_pn_match_d_s = (adc_data_in == adc_data_pn) ? 1'b1 : 1'b0;
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assign adc_pn_match_z_s = (adc_data_in == 'd0) ? 1'b0 : 1'b1;
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assign adc_pn_match_s = adc_pn_match_d & adc_pn_match_z;
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assign adc_pn_update_s = ~(adc_pn_oos_int ^ adc_pn_match_s);
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assign adc_pn_err_s = ~(adc_pn_oos_int | adc_pn_match_s);
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// pn oos and counters (16 to clear and set).
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assign adc_pn_oos = adc_pn_oos_int;
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assign adc_pn_err = adc_pn_err_int;
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always @(posedge adc_clk) begin
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adc_valid_d <= adc_valid_in;
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adc_pn_match_d <= adc_pn_match_d_s;
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adc_pn_match_z <= adc_pn_match_z_s;
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if (adc_valid_d == 1'b1) begin
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adc_pn_err_int <= adc_pn_err_s;
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if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin
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adc_pn_oos_int <= ~adc_pn_oos_int;
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end
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if (adc_pn_update_s == 1'b1) begin
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adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
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end else begin
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adc_pn_oos_count <= 'd0;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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