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The axi_dmac can issue up to FIFO_SIZE read and write requests in parallel. This is done in order to maximize throughput and compensate for for latency. Set the {read,write}IssuingCapability properties accordingly on the AXI master interfaces. Otherwise qsys might decide to insert bridges that artificially limit the number of requests, which in turn might affect performance. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md |
README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
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