627 lines
21 KiB
Verilog
627 lines
21 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module axi_dmac (
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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output s_axi_awready,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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output s_axi_arready,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// Interrupt
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output reg irq,
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// Master AXI interface
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input m_dest_axi_aclk,
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input m_dest_axi_aresetn,
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input m_src_axi_aclk,
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input m_src_axi_aresetn,
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// Write address
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output [31:0] m_dest_axi_awaddr,
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output [7-(4*C_DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
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output [ 2:0] m_dest_axi_awsize,
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output [ 1:0] m_dest_axi_awburst,
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output [ 2:0] m_dest_axi_awprot,
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output [ 3:0] m_dest_axi_awcache,
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output m_dest_axi_awvalid,
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input m_dest_axi_awready,
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// Write data
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output [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
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output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
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input m_dest_axi_wready,
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output m_dest_axi_wvalid,
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output m_dest_axi_wlast,
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// Write response
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input m_dest_axi_bvalid,
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input [ 1:0] m_dest_axi_bresp,
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output m_dest_axi_bready,
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// Unused read interface
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output m_dest_axi_arvalid,
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output [31:0] m_dest_axi_araddr,
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output [7-(4*C_DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
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output [ 2:0] m_dest_axi_arsize,
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output [ 1:0] m_dest_axi_arburst,
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output [ 3:0] m_dest_axi_arcache,
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output [ 2:0] m_dest_axi_arprot,
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input m_dest_axi_arready,
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input m_dest_axi_rvalid,
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input [ 1:0] m_dest_axi_rresp,
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input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
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output m_dest_axi_rready,
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// Read address
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input m_src_axi_arready,
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output m_src_axi_arvalid,
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output [31:0] m_src_axi_araddr,
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output [7-(4*C_DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
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output [ 2:0] m_src_axi_arsize,
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output [ 1:0] m_src_axi_arburst,
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output [ 2:0] m_src_axi_arprot,
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output [ 3:0] m_src_axi_arcache,
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// Read data and response
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input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
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output m_src_axi_rready,
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input m_src_axi_rvalid,
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input [ 1:0] m_src_axi_rresp,
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// Unused write interface
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output m_src_axi_awvalid,
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output [31:0] m_src_axi_awaddr,
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output [7-(4*C_DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
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output [ 2:0] m_src_axi_awsize,
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output [ 1:0] m_src_axi_awburst,
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output [ 3:0] m_src_axi_awcache,
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output [ 2:0] m_src_axi_awprot,
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input m_src_axi_awready,
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output m_src_axi_wvalid,
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output [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
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output [(C_DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
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output m_src_axi_wlast,
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input m_src_axi_wready,
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input m_src_axi_bvalid,
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input [ 1:0] m_src_axi_bresp,
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output m_src_axi_bready,
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// Slave streaming AXI interface
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input s_axis_aclk,
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output s_axis_ready,
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input s_axis_valid,
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input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
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input [0:0] s_axis_user,
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// Master streaming AXI interface
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input m_axis_aclk,
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input m_axis_ready,
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output m_axis_valid,
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output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
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// Input FIFO interface
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input fifo_wr_clk,
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input fifo_wr_en,
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input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
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output fifo_wr_overflow,
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input fifo_wr_sync,
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output fifo_wr_xfer_req,
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// Input FIFO interface
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input fifo_rd_clk,
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input fifo_rd_en,
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output fifo_rd_valid,
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output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
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output fifo_rd_underflow
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);
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parameter PCORE_ID = 0;
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parameter C_DMA_DATA_WIDTH_SRC = 64;
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parameter C_DMA_DATA_WIDTH_DEST = 64;
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parameter C_DMA_LENGTH_WIDTH = 24;
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parameter C_2D_TRANSFER = 1;
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parameter C_CLKS_ASYNC_REQ_SRC = 1;
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parameter C_CLKS_ASYNC_SRC_DEST = 1;
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parameter C_CLKS_ASYNC_DEST_REQ = 1;
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parameter C_AXI_SLICE_DEST = 0;
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parameter C_AXI_SLICE_SRC = 0;
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parameter C_SYNC_TRANSFER_START = 0;
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parameter C_CYCLIC = 1;
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parameter C_DMA_AXI_PROTOCOL_DEST = 0;
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parameter C_DMA_AXI_PROTOCOL_SRC = 0;
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parameter C_DMA_TYPE_DEST = 0;
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parameter C_DMA_TYPE_SRC = 2;
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parameter C_MAX_BYTES_PER_BURST = 128;
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parameter C_FIFO_SIZE = 4; // In bursts
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localparam DMA_TYPE_AXI_MM = 0;
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localparam DMA_TYPE_AXI_STREAM = 1;
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localparam DMA_TYPE_FIFO = 2;
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localparam PCORE_VERSION = 'h00040061;
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localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
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localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
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// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
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localparam BYTES_PER_BEAT_WIDTH_DEST = C_DMA_DATA_WIDTH_DEST > 1024 ? 8 :
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C_DMA_DATA_WIDTH_DEST > 512 ? 7 :
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C_DMA_DATA_WIDTH_DEST > 256 ? 6 :
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C_DMA_DATA_WIDTH_DEST > 128 ? 5 :
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C_DMA_DATA_WIDTH_DEST > 64 ? 4 :
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C_DMA_DATA_WIDTH_DEST > 32 ? 3 :
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C_DMA_DATA_WIDTH_DEST > 16 ? 2 :
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C_DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
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localparam BYTES_PER_BEAT_WIDTH_SRC = C_DMA_DATA_WIDTH_SRC > 1024 ? 8 :
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C_DMA_DATA_WIDTH_SRC > 512 ? 7 :
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C_DMA_DATA_WIDTH_SRC > 256 ? 6 :
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C_DMA_DATA_WIDTH_SRC > 128 ? 5 :
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C_DMA_DATA_WIDTH_SRC > 64 ? 4 :
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C_DMA_DATA_WIDTH_SRC > 32 ? 3 :
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C_DMA_DATA_WIDTH_SRC > 16 ? 2 :
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C_DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
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// Register interface signals
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reg [31:0] up_rdata = 'd0;
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reg up_ack = 1'b0;
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wire up_wr;
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wire up_sel;
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wire [31:0] up_wdata;
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wire [11:0] up_addr;
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wire up_write;
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// Scratch register
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reg [31:0] up_scratch = 'h00;
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// Control bits
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reg up_enable = 'h00;
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reg up_pause = 'h00;
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// Start and end of transfer
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wire up_eot; // Asserted for one cycle when a transfer has been completed
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wire up_sot; // Asserted for one cycle when a transfer has been queued
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// Interupt handling
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reg [1:0] up_irq_mask = 'h3;
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reg [1:0] up_irq_source = 'h0;
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wire [1:0] up_irq_pending;
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wire [1:0] up_irq_trigger;
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wire [1:0] up_irq_source_clear;
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// DMA transfer signals
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reg up_dma_req_valid = 1'b0;
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wire up_dma_req_ready;
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reg [1:0] up_transfer_id;
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reg [1:0] up_transfer_id_eot;
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reg [3:0] up_transfer_done_bitmap;
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reg [31:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
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reg [31:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00;
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reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00;
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reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
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reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
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reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
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reg up_dma_cyclic = C_CYCLIC;
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wire up_dma_sync_transfer_start = C_SYNC_TRANSFER_START ? 1'b1 : 1'b0;
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// ID signals from the DMAC, just for debugging
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wire [2:0] dest_request_id;
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wire [2:0] dest_data_id;
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wire [2:0] dest_address_id;
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wire [2:0] dest_response_id;
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wire [2:0] src_request_id;
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wire [2:0] src_data_id;
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wire [2:0] src_address_id;
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wire [2:0] src_response_id;
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wire [7:0] dbg_status;
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up_axi #(
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.PCORE_ADDR_WIDTH (12)
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) i_up_axi (
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.up_rstn(s_axi_aresetn),
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.up_clk(s_axi_aclk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wr(up_wr),
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.up_sel(up_sel),
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.up_addr(up_addr),
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.up_wdata(up_wdata),
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.up_rdata(up_rdata),
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.up_ack(up_ack)
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);
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// IRQ handling
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assign up_irq_pending = ~up_irq_mask & up_irq_source;
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assign up_irq_trigger = {up_eot, up_sot};
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assign up_irq_source_clear = (up_write == 1'b1 && up_addr == 12'h021) ? up_wdata[1:0] : 0;
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always @(posedge s_axi_aclk)
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begin
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if (s_axi_aresetn == 1'b0)
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irq <= 1'b0;
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else
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irq <= |up_irq_pending;
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end
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always @(posedge s_axi_aclk)
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begin
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if (s_axi_aresetn == 1'b0) begin
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up_irq_source <= 2'b00;
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end else begin
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up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
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end
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end
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// Register Interface
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assign up_write = up_wr & up_sel;
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always @(posedge s_axi_aclk)
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begin
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if (s_axi_aresetn == 1'b0) begin
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up_enable <= 'h00;
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up_pause <= 'h00;
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up_dma_src_address <= 'h00;
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up_dma_dest_address <= 'h00;
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up_dma_y_length <= 'h00;
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up_dma_x_length <= 'h00;
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up_dma_dest_stride <= 'h00;
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up_dma_src_stride <= 'h00;
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up_irq_mask <= 3'b11;
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up_dma_req_valid <= 1'b0;
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up_scratch <= 'h00;
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up_ack <= 1'b0;
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end else begin
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up_ack <= up_sel;
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if (up_enable == 1'b1) begin
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if (up_write && up_addr == 12'h102) begin
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up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
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end else if (up_sot) begin
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up_dma_req_valid <= 1'b0;
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end
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end else begin
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up_dma_req_valid <= 1'b0;
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end
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if (up_write) begin
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case (up_addr)
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12'h002: up_scratch <= up_wdata;
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12'h020: up_irq_mask <= up_wdata;
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12'h100: {up_pause, up_enable} <= up_wdata[1:0];
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12'h103: if (C_CYCLIC) up_dma_cyclic <= up_wdata[0];
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12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
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12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
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12'h106: up_dma_x_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
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12'h107: up_dma_y_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
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12'h108: up_dma_dest_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
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12'h109: up_dma_src_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
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endcase
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end
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end
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end
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always @(posedge s_axi_aclk)
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begin
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if (s_axi_aresetn == 1'b0) begin
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up_rdata <= 'h00;
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end else begin
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case (up_addr)
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12'h000: up_rdata <= PCORE_VERSION;
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12'h001: up_rdata <= PCORE_ID;
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12'h002: up_rdata <= up_scratch;
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12'h020: up_rdata <= up_irq_mask;
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12'h021: up_rdata <= up_irq_pending;
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12'h022: up_rdata <= up_irq_source;
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12'h100: up_rdata <= {up_pause, up_enable};
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12'h101: up_rdata <= up_transfer_id;
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12'h102: up_rdata <= up_dma_req_valid;
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12'h103: up_rdata <= {31'h00, up_dma_cyclic}; // Flags
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12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
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12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
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12'h106: up_rdata <= up_dma_x_length;
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12'h107: up_rdata <= C_2D_TRANSFER ? up_dma_y_length : 'h00;
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12'h108: up_rdata <= C_2D_TRANSFER ? up_dma_dest_stride : 'h00;
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12'h109: up_rdata <= C_2D_TRANSFER ? up_dma_src_stride : 'h00;
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12'h10a: up_rdata <= up_transfer_done_bitmap;
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12'h10b: up_rdata <= up_transfer_id_eot;
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12'h10c: up_rdata <= 'h00; // Status
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12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
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12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
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12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id,
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1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id};
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|
12'h110: up_rdata <= dbg_status;
|
|
default: up_rdata <= 'h00;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// Request ID and Request done bitmap handling
|
|
always @(posedge s_axi_aclk)
|
|
begin
|
|
if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin
|
|
up_transfer_id <= 'h0;
|
|
up_transfer_id_eot <= 'h0;
|
|
up_transfer_done_bitmap <= 'h0;
|
|
end begin
|
|
if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin
|
|
up_transfer_id <= up_transfer_id + 1'b1;
|
|
up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
|
|
end
|
|
if (up_eot == 1'b1) begin
|
|
up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
|
|
up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
wire dma_req_valid;
|
|
wire dma_req_ready;
|
|
wire [31:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
|
|
wire [31:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
|
|
wire [C_DMA_LENGTH_WIDTH-1:0] dma_req_length;
|
|
wire dma_req_eot;
|
|
wire dma_req_sync_transfer_start;
|
|
wire up_req_eot;
|
|
|
|
assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
|
|
assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot;
|
|
|
|
|
|
generate if (C_2D_TRANSFER == 1) begin
|
|
|
|
dmac_2d_transfer #(
|
|
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
|
|
.C_BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
|
|
.C_BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
|
|
) i_2d_transfer (
|
|
.req_aclk(s_axi_aclk),
|
|
.req_aresetn(s_axi_aresetn),
|
|
|
|
.req_eot(up_req_eot),
|
|
|
|
.req_valid(up_dma_req_valid),
|
|
.req_ready(up_dma_req_ready),
|
|
.req_dest_address(up_dma_dest_address),
|
|
.req_src_address(up_dma_src_address),
|
|
.req_x_length(up_dma_x_length),
|
|
.req_y_length(up_dma_y_length),
|
|
.req_dest_stride(up_dma_dest_stride),
|
|
.req_src_stride(up_dma_src_stride),
|
|
.req_sync_transfer_start(up_dma_sync_transfer_start),
|
|
|
|
.out_req_valid(dma_req_valid),
|
|
.out_req_ready(dma_req_ready),
|
|
.out_req_dest_address(dma_req_dest_address),
|
|
.out_req_src_address(dma_req_src_address),
|
|
.out_req_length(dma_req_length),
|
|
.out_req_sync_transfer_start(dma_req_sync_transfer_start),
|
|
.out_eot(dma_req_eot)
|
|
);
|
|
|
|
end else begin
|
|
|
|
assign dma_req_valid = up_dma_req_valid;
|
|
assign up_dma_req_ready = dma_req_ready;
|
|
assign dma_req_dest_address = up_dma_dest_address;
|
|
assign dma_req_src_address = up_dma_src_address;
|
|
assign dma_req_length = up_dma_x_length;
|
|
assign dma_req_sync_transfer_start = up_dma_sync_transfer_start;
|
|
assign up_req_eot = dma_req_eot;
|
|
|
|
end endgenerate
|
|
|
|
dmac_request_arb #(
|
|
.C_DMA_DATA_WIDTH_SRC(C_DMA_DATA_WIDTH_SRC),
|
|
.C_DMA_DATA_WIDTH_DEST(C_DMA_DATA_WIDTH_DEST),
|
|
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
|
|
.C_BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
|
|
.C_BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
|
|
.C_DMA_TYPE_DEST(C_DMA_TYPE_DEST),
|
|
.C_DMA_TYPE_SRC(C_DMA_TYPE_SRC),
|
|
.C_CLKS_ASYNC_REQ_SRC(C_CLKS_ASYNC_REQ_SRC),
|
|
.C_CLKS_ASYNC_SRC_DEST(C_CLKS_ASYNC_SRC_DEST),
|
|
.C_CLKS_ASYNC_DEST_REQ(C_CLKS_ASYNC_DEST_REQ),
|
|
.C_AXI_SLICE_DEST(C_AXI_SLICE_DEST),
|
|
.C_AXI_SLICE_SRC(C_AXI_SLICE_SRC),
|
|
.C_MAX_BYTES_PER_BURST(C_MAX_BYTES_PER_BURST),
|
|
.C_FIFO_SIZE(C_FIFO_SIZE)
|
|
) i_request_arb (
|
|
.req_aclk(s_axi_aclk),
|
|
.req_aresetn(s_axi_aresetn),
|
|
|
|
.enable(up_enable),
|
|
.pause(up_pause),
|
|
|
|
.req_valid(dma_req_valid),
|
|
.req_ready(dma_req_ready),
|
|
.req_dest_address(dma_req_dest_address),
|
|
.req_src_address(dma_req_src_address),
|
|
.req_length(dma_req_length),
|
|
.req_sync_transfer_start(dma_req_sync_transfer_start),
|
|
|
|
.eot(dma_req_eot),
|
|
|
|
|
|
.m_dest_axi_aclk(m_dest_axi_aclk),
|
|
.m_dest_axi_aresetn(m_dest_axi_aresetn),
|
|
.m_src_axi_aclk(m_src_axi_aclk),
|
|
.m_src_axi_aresetn(m_src_axi_aresetn),
|
|
|
|
|
|
.m_axi_awaddr(m_dest_axi_awaddr),
|
|
.m_axi_awlen(m_dest_axi_awlen),
|
|
.m_axi_awsize(m_dest_axi_awsize),
|
|
.m_axi_awburst(m_dest_axi_awburst),
|
|
.m_axi_awprot(m_dest_axi_awprot),
|
|
.m_axi_awcache(m_dest_axi_awcache),
|
|
.m_axi_awvalid(m_dest_axi_awvalid),
|
|
.m_axi_awready(m_dest_axi_awready),
|
|
|
|
|
|
.m_axi_wdata(m_dest_axi_wdata),
|
|
.m_axi_wstrb(m_dest_axi_wstrb),
|
|
.m_axi_wready(m_dest_axi_wready),
|
|
.m_axi_wvalid(m_dest_axi_wvalid),
|
|
.m_axi_wlast(m_dest_axi_wlast),
|
|
|
|
|
|
.m_axi_bvalid(m_dest_axi_bvalid),
|
|
.m_axi_bresp(m_dest_axi_bresp),
|
|
.m_axi_bready(m_dest_axi_bready),
|
|
|
|
|
|
.m_axi_arready(m_src_axi_arready),
|
|
.m_axi_arvalid(m_src_axi_arvalid),
|
|
.m_axi_araddr(m_src_axi_araddr),
|
|
.m_axi_arlen(m_src_axi_arlen),
|
|
.m_axi_arsize(m_src_axi_arsize),
|
|
.m_axi_arburst(m_src_axi_arburst),
|
|
.m_axi_arprot(m_src_axi_arprot),
|
|
.m_axi_arcache(m_src_axi_arcache),
|
|
|
|
|
|
.m_axi_rdata(m_src_axi_rdata),
|
|
.m_axi_rready(m_src_axi_rready),
|
|
.m_axi_rvalid(m_src_axi_rvalid),
|
|
.m_axi_rresp(m_src_axi_rresp),
|
|
|
|
|
|
.s_axis_aclk(s_axis_aclk),
|
|
.s_axis_ready(s_axis_ready),
|
|
.s_axis_valid(s_axis_valid),
|
|
.s_axis_data(s_axis_data),
|
|
.s_axis_user(s_axis_user),
|
|
|
|
|
|
.m_axis_aclk(m_axis_aclk),
|
|
.m_axis_ready(m_axis_ready),
|
|
.m_axis_valid(m_axis_valid),
|
|
.m_axis_data(m_axis_data),
|
|
|
|
|
|
.fifo_wr_clk(fifo_wr_clk),
|
|
.fifo_wr_en(fifo_wr_en),
|
|
.fifo_wr_din(fifo_wr_din),
|
|
.fifo_wr_overflow(fifo_wr_overflow),
|
|
.fifo_wr_sync(fifo_wr_sync),
|
|
.fifo_wr_xfer_req(fifo_wr_xfer_req),
|
|
|
|
|
|
.fifo_rd_clk(fifo_rd_clk),
|
|
.fifo_rd_en(fifo_rd_en),
|
|
.fifo_rd_valid(fifo_rd_valid),
|
|
.fifo_rd_dout(fifo_rd_dout),
|
|
.fifo_rd_underflow(fifo_rd_underflow),
|
|
|
|
// DBG
|
|
.dbg_dest_request_id(dest_request_id),
|
|
.dbg_dest_address_id(dest_address_id),
|
|
.dbg_dest_data_id(dest_data_id),
|
|
.dbg_dest_response_id(dest_response_id),
|
|
.dbg_src_request_id(src_request_id),
|
|
.dbg_src_address_id(src_address_id),
|
|
.dbg_src_data_id(src_data_id),
|
|
.dbg_src_response_id(src_response_id),
|
|
.dbg_status(dbg_status)
|
|
);
|
|
|
|
assign m_dest_axi_arvalid = 1'b0;
|
|
assign m_dest_axi_rready = 1'b0;
|
|
assign m_dest_axi_araddr = 'h0;
|
|
assign m_dest_axi_arlen = 'h0;
|
|
assign m_dest_axi_arsize = 'h0;
|
|
assign m_dest_axi_arburst = 'h0;
|
|
assign m_dest_axi_arcache = 'h0;
|
|
assign m_dest_axi_arprot = 'h0;
|
|
|
|
assign m_src_axi_awvalid = 1'b0;
|
|
assign m_src_axi_wvalid = 1'b0;
|
|
assign m_src_axi_bready = 1'b0;
|
|
assign m_src_axi_awvalid = 'h0;
|
|
assign m_src_axi_awaddr = 'h0;
|
|
assign m_src_axi_awlen = 'h0;
|
|
assign m_src_axi_awsize = 'h0;
|
|
assign m_src_axi_awburst = 'h0;
|
|
assign m_src_axi_awcache = 'h0;
|
|
assign m_src_axi_awprot = 'h0;
|
|
assign m_src_axi_wvalid = 'h0;
|
|
assign m_src_axi_wdata = 'h0;
|
|
assign m_src_axi_wstrb = 'h0;
|
|
assign m_src_axi_wlast = 'h0;
|
|
|
|
endmodule
|