10 lines
500 B
Plaintext
10 lines
500 B
Plaintext
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "4.000 ns" -name rx_clk_250mhz [get_ports {rx_clk_in}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -from [get_registers system_bd:i_system_bd|axi_ad9361:axi_ad9361|axi_ad9361_lvds_if:i_dev_if|axi_ad9361_lvds_if_10:i_axi_ad9361_lvds_if_10|locked_int]
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