54 lines
1.7 KiB
Tcl
54 lines
1.7 KiB
Tcl
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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#
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# Parameter description:
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# JESD_MODE : Used link layer encoder mode
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# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
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# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
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#
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# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
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# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
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# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode
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# Encoding is:
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# 0 - CPLL
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# 1 - QPLL0
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# 2 - QPLL1
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# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
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# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
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#
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#
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# !!! For this carrier only 8B10B mode is supported !!!
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#
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adi_project ad9081_fmca_ebz_zcu102 0 [list \
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JESD_MODE 8B10B \
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RX_JESD_M 8 \
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RX_JESD_L 4 \
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RX_JESD_S 1 \
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RX_JESD_NP 16 \
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RX_NUM_LINKS 1 \
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TX_JESD_M 8 \
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TX_JESD_L 4 \
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TX_JESD_S 1 \
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TX_JESD_NP 16 \
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TX_NUM_LINKS 1 \
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]
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adi_project_files ad9081_fmca_ebz_zcu102 [list \
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"system_top.v" \
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"system_constr.xdc"\
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"timing_constr.xdc"\
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"../../../library/common/ad_3w_spi.v"\
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
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adi_project_run ad9081_fmca_ebz_zcu102
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